EIPC Technical Snapshot Review: Semi-additive Processes

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The development of ultra-high-density PCBs and packaging substrates using semi-additive and additive manufacturing processes was the theme of the 13th Technical Snapshot webinar presented by EIPC on November 24. It was introduced and moderated by technical director Tarja Rapala-Virtanen.

Daniel Schulze, application engineering manager at Dyconex in Switzerland, gave the opening presentation, “Advanced high density rigid packaging substrates for RF and miniaturization.” He explained that with their long-established capabilities in ultra-high-density PCBs in flex, rigid-flex and rigid multilayer technologies, it was logical for Dyconex to apply their expertise to the development of specialist IC substrates.


He illustrated the diversity of component packaging and how it had advanced from the plastic ball grid arrays of the 1990s to the 3D stacked-die integrated circuits, fan-out-chip-on-substrate packages and silicon photonics devices of the present day.

“Something has to shrink and this is often the PCB,” he said as he discussed the motivation for higher density and the factors that are driving the industry toward thinner devices while avoiding any compromise of reliability or performance.

He reviewed current requirements for packaging substrates, typically accommodating larger chips with increased connectivity and capable of higher frequency operation, and presented a long list of desirable physical, mechanical, thermal and electrical properties of materials, together with miniaturisation of circuit features.


Dyconex has designed a composite packaging-demonstrator PCB, which incorporated pattern features for resolution, any-layer stacked blind vias, wire bonding pitch, flip chip pitch, resistors, RF features, and interconnect stress testing. This was used to characterise and evaluate a range of glass-reinforced and non-reinforced materials.

Subtractive processing was capable of achieving lines and spaces down to 18 microns; modified semi-additive processing could achieve 10 microns. For laser-drilled any-layer stacked blind vias, 50-micron vias in 150-micron pads are now routine and state-of-the-art was 40-micron vias in 90-micron pads. Schulze described how interconnect stress testing has been used to demonstrate the reliability of a 10-layer BT-epoxy stacked blind via design with 30-micron dielectric layers and 50-micron vias in 120-micron pads.

He showed examples of substrates developed for special applications: a high-layer-count HDI interposer measuring more than 30 mm uses an ultra-dense substrate for a 150-micron pitch ASIC, a package-on-package module with via frame and mould fill, and a super-miniaturization folded package based on flexible polyimide. Dyconex can offer engineering support and a fast prototype service for packaging substrates in materials and designs equivalent to high-end Asian products, and manufacture quick-turn low- to mid-volume product.


Staying with the subject of high-density substrates, Lars Böttcher, head of group for embedding and substrates with Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration in Berlin, discussed the development of fan-out and panel-level packaging technologies.

He began with an introduction to the processing of redistribution layers, those copper interconnects that electrically link one part of a semiconductor package to another and reviewed semi-additive processes as routes toward reducing line pitch. Modified semi-additive processing, mSAP, on a base of 1.3 to 3 microns of clad foil plus 1 to 2 microns of electroless copper, was used for lines and space above 20 microns. Semi-additive processing, SAP, on a base of 1 to 2 microns of electroless copper, was capable of achieving lines and spaces in the range of 10-20 microns.

Advanced semi-additive processing, aSAP on a base of 50 to 500 nanometres of vapour deposited copper, could achieve lines and spaces in the region of 10-5 microns. Böttcher described the process flow: Typical substrate was based on non-glass-reinforced, filled or non-filled dielectric, provided in different forms, dry film being the most convenient. This could be photo-imaged or laser drilled to form vias, then coated with barrier and seed layers of titanium and copper by vapour deposition. High-resolution liquid or dry film photoresist was applied and structured by direct imaging or adaptive imaging, followed by semi-additive copper plating, removal of the photoresist and differential etching.

He demonstrated a process sequence for the formation of a redistribution layer with plated copper traces featuring 5-micron lines and spaces, for an embedding application.

For vertical interconnection, the basic options are laser or photo vias, and Böttcher reviewed the benefits and limitations of each. Photo vias can give higher registration accuracy and resolution, and the process is faster but there are process limitations in application and development when using photoimageable dielectric materials. He showed microsection examples of vias formed by both techniques. A third option, more recently introduced, was plasma vias although there were still some issues of plasma etching speed, hole shape and uniformity to be considered.

Böttcher explored the concept of embedding of dies in panel-level packaging, using a PCB laminate core in order to limit die shift and offer improved handling stability. He showed a schematic process sequence where dies with copper pillars are placed in pre-formed cavities in the PCB core, retained by adhesive tape. Vacuum lamination with dielectric film effectively embed the dies from one side, then the adhesive film is removed to expose the copper pillars and these are embedded by a second vacuum lamination. Vias are then formed by laser, photo or plasma, and redistribution layers formed by SAP copper plating before separating the packages. He showed actual examples at each process stage and emphasised that adaptive imaging is key to overcoming the challenges of alignment and registration.

Michael_Schleicher.jpgIn her preface to the final presentation, Rapala-Virtanen commented that additive manufacturing principles will be progressively adopted within the industry during the coming years, and new manufacturing approaches will be established. She introduced Michael Schleicher, printed circuit design specialist with Semikron Elektronik in Nuremberg and member of the board of directors of FED, the German PCB designers’ council, who described a disruptive approach in the design and tool chain of additively manufactured circuit boards.

Having reviewed basic module technologies for die attach and die connection established at Semikron, he focused on silver sintering and explained how inkjet techniques have been developed and optimised for the accurate deposition of functional silver ink in complex patterns. Market forecasts indicate substantial growth in the use of inkjet technologies in additively manufactured electronics. Schleicher showed examples of fast turnaround prototype multilayer circuits with 70-micron lines and 100-micron spaces, produced on a proprietary three-dimensional printer using nanotechnology-based conductive and dielectric ink products.

Additive manufacturing also enables the incorporation of many third-dimension features into traditional uniform-thickness circuit configurations and opened-up an enormous range of design options, offering a disruptive approach for future layout solutions.

Schleicher’s design feature illustrations included possibilities such as three-dimensional substrate shaping, any-layer routing, any-angle routing, any-angle teardrops, any-angle holes, via-less routing, vertical fan-out, real twisted-pair routing and many harness design and shielding options.

To realise the benefits of such technologies, existing process-flow concepts, eCAD tools, and data formats will have to change. The FED working group on three-dimensional electronics technology, Arbeitskreis 3D-Elektronik, founded in 2016, is studying feasibility and gathering knowledge on data formats, design tools, and technical terms.

Schleicher’s schematic PCB tool chain for additively manufactured substrates showed a design flow from two-dimensional library information through two-dimensional eCAD, followed by conversion to three-dimensional using mCAD tools, followed by the generation of production data for three-dimensional manufacture.

The working group proposed a classification matrix for additively manufactured electronics, based on surface or shape, base material, functional fluid and manufacturing data. Complexity is ranked as a series of levels from one to five. Level 1 denotes a flat-surfaced circuit made from a single material. Level 5 represented a fully three-dimensional printed device incorporating embedded and pick-and-place components.

A busy question-and-answer session was expertly managed by Rapala-Virtanen before she brought the webinar to a close, announcing that the Technical Snapshots will continue in 2022. She was also delighted to announce the first live EIPC event since lock-down—a conference in Frankfurt on February 10—is definitely something to look forward to.


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