Test Strategies and Pain Points


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Bert Horner of The Test Connection, Inc., a test engineering service provider, shares his insights on the trends and challenges for test and inspection. He centers his discussion around common challenges in the industry, and the importance of setting up your test and inspection strategy.

Barry Matties: Bert, thanks for joining us today. The Test Connection is a generational business, correct?

Bert Horner: Yes. We celebrate our 41st year this year.

Matties: Congratulations. That’s fantastic. Your father started the business?

Horner: Yes, sir. In 1980.

Matties: That’s wonderful. From those many years, what trends are you seeing in terms of repeating defects in manufacturing, or what your test data is revealing? What are the common mistakes?

Horner: We’ve seen the bar chart until we’re all sick in the stomach of seeing shorts and opens. Solder splashes are probably the most common. The other issues are orientation and wrong value passives. Then it goes over to the lower levels where they say the device is the wrong one and is not performing up to spec. They’re the low opportunities of electrical tests. One thing we see with electrical test—when you get through the AOI and the X-ray, and you’re getting into flying probe and in-circuit ICT—is the bed-of-nails ICT. We’re encroaching on some functional and design test. That helps justify the cost of a bed-of-nails fixture or a flying probe. More people are incorporating what we call cluster or functional testing at those test solutions.

Matties: What challenges do you see fabricators generally having in test and inspection?

Horner: We see some challenges with design for test. The biggest challenge is giving access to the key points and understanding a test strategy prior to the assembly being built. We feel there’s a lack of communication among design, manufacturing, and test that creates an opportunity for test engineering to put their wishes into the design. There’s a disconnect between the internal and external test engineering groups and the design group.

Matties: Are there differences between test strategies based on the EMS provider that you’re using, or is there a standard that designers should be following?

Horner: There’s not really a standard to follow other than understanding what your EMS partner must support. What solutions do they have? Do they have an X-ray? Do they have an AOI? Do they have an in-circuit tester? Do they have a flying prober? Understanding what your partner has and what they have available for test and inspection needs to be communicated upstream or the design group needs to specify it: “This is a test strategy based on this AOI, this X-ray, and this electrical test.”

Matties: So, not only does the design layout person need to be an SI and stackup expert, now they must be an authority on test strategies as well.

Horner: They must have a good understanding of what they’re trying to accomplish. We see a lot of designers working with a project engineer, and sometimes that role falls onto a project engineer or a program manager of a specific project. That understanding needs to be somewhere down the food chain where the design is in a soft stage and they’re coming up with a plan.

Matties: Now, going back to those common problems, such as splashing, opens, and shorts, what feedback or data do you provide to the manufacturers that will help them improve their process, or is there such a cycle?

Horner: For our test services, we incorporate a summary where, by serial number, they can see what the common faults are. If they have some quality management system (QMS) at the contract house, they’re reading in the data, and they can see trends quickly. But we do a summary when we’re testing product under contract test services.

Nolan Johnson: Bert, where does a project manager, project engineer, or designer go to find out? Where are their resources for design for test?

Horner: Most test partners have created their own, and they’re all based on a very similar design for tests guidelines, whether it’s bed-of-nails, flying probe, or boundary scan. There are some common papers for most partners (we’re one of them), and we have a boundary scan, an ICT, and a flying probe guideline for design for tests. There are also products in the market. ASTER Technologies has TestWay. Mentor has Text Expert. These are tools that are encroaching on that schematic level review, where everybody has a solution that looks for access. Whether they use it is a different question, but we are seeing people in the market look at the schematic level design for test: Automated Tool, TestWay, Test Expert. I know we have both products here, and when you’re looking at the schematic level, you’re seeing where the controllability of a circuit is, where you have access, and you have control of a circuit so you can isolate down on to a net, a pin, and a device.

Johnson: Are these tools a bit like using a DRC checker after the fact?

Horner: No, they’re more upfront. While the electrical engineer is laying out a schematic, even before they lay out a board, they can be putting DFT into the card and it’s catching it before it goes out to a PCB layout. You can identify key nets and net pins that you must have access to. So, when you have circuitry where you have RF, high-speed digital, or microwave, and you can’t put in test points or control circuits, at least on the peripheral circuitry, you can get access. You may have to only do more of a functional test on those high-speed areas that you can’t pick up using traditional ICT flying probe and even boundary skin.

To read this entire conversation, which appeared in the November 2021 issue of SMT007 Magazine, click here.

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