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Q. What is the best method for tying vias to ground and power planes for bypass capacitors when using multiple caps of different values for one component power pin?
Rick Hartley: When connecting bypass/decoupling capacitors to power/ground planes, each capacitor should be connected with its own set of vias. Sharing vias between caps should be avoided unless absolutely necessary (in cases where component density is extremely high). The best connection arrangement is the one with the lowest via pair inductance. Low via pair inductance is achieved when the power and the ground vias are very close together and very near the capacitor pins. Large vias that are far apart have higher inductance than small vias that are close together. Close spacing, not large size, is the key to low via inductance.
Using multiple values of bypass/decoupling capacitors is generally not a great idea. Doing so can, and often does, lead to problems with anti-resonant peaks in the power bus impedance, caused by the parallel resonance of the capacitance of one device relative to the inductance of another device of a different value. Multiple values can be implemented successfully, but will require extensive simulation with a high-end power bus simulator, to minimize anti-resonant peaks. High power bus impedance at any frequency can cause SI and EMI issues.
Heidi Barnes: First, capacitors should be selected for flat matched impedance and not just “factor of 10” old-school leveraging. If a large cap is placed next to a small cap one can have a Pi resonator between the ESL of the large cap and the C of the small cap. Selecting the right ESR to achieve a target Z will help reduce the number of caps by maximizing the bandwidth of power delivery for each capacitor before the next capacitor takes over. Next, as your question asks, is the importance of ground and power vias to have low inductance to the component power pin. The best way to do this is to start with a thin dielectric between the power and ground planes to form a parallel plate with small loop inductance. Three mils is typically sufficient and can significantly reduce both the via loop inductance as well as the path inductance to the load. Finally, using capacitor footprint topology that gets the power and ground return vias as close as possible will help reduce the inductance further. To maximize the high frequency bandwidth, the smallest capacitor should be placed as close as possible to the power pin. In the case of BGA devices this is typically on the opposite side of the part directly across the power and ground vias to the BGA.
Eric Bogatin: Why use different value capacitors on the same power pin? As a general rule, never share power or return vias.
Cherie Litson: Put the smallest value cap closest to the power pin. Where the via goes depends upon the type of signal. RF signals prefer to have the via to the plane after the pin connects to the cap. Digital signals prefer to have the via go directly to the plane and then to the cap.
Lee Ritchey: Since virtually all capacitors are surface mount, there is no need for thermal ties between the power vias and the planes. All a designer needs to do is drill a hole in the appropriate plane and make a full contact with the plated through-hole.
Carl Schattke: The smallest inductive loop is going to be the least parasitic. In order for the energy to flow in a circuit, the inductive force must be overcome before the voltage will rise. Basically, the spin happens before the push. To reduce the time and energy this takes, we want to minimize the area that has to be energized. This area is going to be the 3D gap between the power trace and the return path. Closer is always better electrically, but if it’s too close, though, you start to get into the manufacturing concerns of copper-to-copper plating limitations based on copper weights and etch processing, not to mention the hole-to-hole limitations of cracked laminate, and potential CAF problems. Ideally, we place the vias at the edge of the manufacturing tolerances that will not add cost or reduce reliability.
Chris Young: In general, when dealing with multiple decoupling capacitors (0.1 mF, 0.01 mF, 0.001 mF values are common) per power pin, a typical approach is to put the smallest-value capacitor closest to the power pin and the larger value as close to the smaller capacitor as possible. This is usually done to shunt noise or interference signals away from the power input of a device. Power vias are usually placed at the largest value capacitor and a trace drawn directly (as possible) from the via to the power pin through the pads of the capacitors. Each decoupling capacitor should have an independent ground via placed as close as possible to the pads. Keep in mind that traces and space between components should be as small as possible as well while maintaining distances allow for manufacturing capabilities. See Figure 1 for a typical placement of decoupling capacitors near a device.
Figure 1: Typical placement of a decoupling capacitor near a device.