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We are living in an age where the demands on electronic product designs are constantly evolving. The IC technology and operating speeds continue to pose significant challenges for teams as they work to develop their products. The increased transistor switching speeds and less forgiving compliance standards make signal integrity and electro-magnetic compliance more difficult to achieve. The status quo seems to have become, “We expect to fail EMC testing.”
What can be done to increase the likelihood of compliance, and proper function? In some cases, the engineering community looks to simulation as a method of evaluating the PCB design. There are certainly a number of powerful tools available, but they are usually expensive and difficult to use properly. These tools are only of value if the transmission lines are not broken. The simulated results often differ from the measured behaviors, forcing model tweaks and lost time. In most cases, you have an incomplete model and inaccurate measurements, which even when reconciled, do not reflect the real behaviors of the design. It is nearly impossible to get good measurements for this purpose. The probes will affect the signal, as does the location in the transmission line where the measurement is taken. Many teams just do not have the bandwidth or expertise to achieve success using this process.
The fundamental issue is that most simulation tools are not capable of evaluating broken transmission lines. (I say “most” because I am not intimately familiar with all of them.) A broken transmission line is a signal or power conductor that is not one dielectric away from ground. If a signal or power conductor is not directly adjacent to a continuous dielectric bounded by a continuous ground conductor, the EM fields do not stay where the design requires. The field will fill the space between the signal conductor and the ground conductor that connects to the power source for the PCB.
The more conductors and dielectrics that are between the signal in question and its ground, the more impact on signal integrity and EMC. There are just not enough nodes in the models. It would require characterizing every change in the transmission line geometry, for not only the signal trace in question, but the other nearby traces and the power supplies for the ICs involved. Once a trace crosses a split in the ground plane, the space involved in the signal transmission expands to include the divergent path of the continuous ground conductor. This increases the time it takes to establish the signal voltage, requiring more wave cycles to achieve the signal levels. Each wave cycle increases crosstalk and possible radiated emissions, which occur at every wavefront. Every other signal crossing the split will also have an expanded space to fill. These signals will then share the space and affect the voltage for each signal. If a power supply is not properly designed, signal integrity is compromised for all the signals using that supply. If a signal is compromised, it affects not only that signal, but other signals in the adjacent areas of the PCB.
To read this entire article, which appeared in the April 2021 issue of Design007 Magazine, click here.