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EIPC’s Technical Snapshots have become increasingly popular monthly events, not the least due to John Ling’s intriguing invitations. Here is the latest: “There is a relatively new word in the English Dictionary, it’s ‘woke.’ We have a new definition, and it is linked to that very important current topic—mental health. WOKE stands for Working On Knowledge Extension, and this can only be achieved by attending an EIPC Webinar. EIPC has always had extremely mentally fit members, which may account for its success, so on 17th March you can have a work-out (actually it will be a work-in as you will be at home) with three of them who will be delighted to share their exercises with you.”
Bringing a specialised technical area into sharp focus, this month’s topic was “5G and the understanding of loss minimisation at the PCB level,” with papers on dielectric material, copper foil, and modelling solutions. The webinar was moderated by EIPC board member Paul Waldner, managing director of Multiline International Europa, who admitted that he had managed to get a haircut especially for the occasion!
Manfred Huschka, vice president global marketing with AGC Multi Material, gave the first presentation, expanding on the statement: “Electrical and mechanical reliability of an RF laminate are key requirements for selection in 77GHz ADAS sensor.” For those of us to whom the company name was not familiar, he explained that AGC was in fact Asahi Glass Company, whose Multi Material division now incorporated Nelco and Taconic. Ironically, his talk centered on non-glass-reinforced laminates, specifically a ceramic-filled PTFE material increasingly used in 77GHz ADAS radar sensors, for which an exponential growth curve was forecast.
A characteristic of this material was an advanced ceramic filler system composed of small round particles, enabling a smoother interface between the dielectric layer and an ultra-low-profile copper foil, with much reduced probability of noise being initiated by filler particles making contact with the foil. He showed graphs of insertion loss against frequency, comparing ultra-low-profile foil, reverse-treated foil, and very-low-profile foil, indicating a significant advantage for the ultra-low-profile foil at frequencies approaching 100GHz. Although the bonding surface of the foil was remarkably smooth, a high peel strength was maintained even after repeated reflow cycles. This was largely attributed to the adhesion characteristics of the resin, and was reassuring news to designers and reliability engineers.
Because there was no woven glass reinforcement, the dielectric properties of the ceramic-filled resin were consistent in all three axes, and weave-related effects were nonexistent. Furthermore, insertion loss showed only a very small frequency drift over large temperature ranges.
PCB fabrication with this material was straightforward, and normal plasma treatment enabled through-holes to be plated with good adhesion. The material had been demonstrated to withstand 288°C solder float for 30 minutes without delamination, and could be used in the fabrication of hybrid multilayers. Huschka showed cross-section examples of plated through-holes and blind vias that had been subjected to 1,000 thermal cycles of -40°C to +140°C with no evidence of failure. The material was already used in the mass production of multiple designs of 77GHz ADAS sensors.
Manfred Huschka, having indicated the benefits of ultra-low-profile copper foil in special low-loss laminates, Julie Mouzon, customer technical service manager with Circuit Foil in Luxembourg, went into greater detail, describing the manufacturing process and discussing the attributes of ultra-flat ED-copper foils dedicated to high-speed digital and RF circuit boards.
Normal ED foil, appropriate for use in the lower frequency ranges, was electro-deposited onto a slowly rotating polished titanium drum, and continuously peeled off. At this stage, the drum side of the foil was smooth and shiny, and the other had a precisely controlled crystalline structure with a matte appearance. This base foil was then processed through a sequence of chemical and electro-chemical processing steps to modify the surface to enhance adhesion to laminating resin, resulting in a slightly roughened surface. At higher frequencies, because of “skin effect,” this roughened surface could result in substantial signal loss.
The challenge was therefore to attain the smoothest copper foil profile while ensuring an acceptable level of peel strength. This was partly achieved by optimising the surface preparation of the titanium drum and by adding specific organic levelling agents to the copper electrolyte, and then by reduction or suppression of the subsequent nodular treatment and the use of silanes and other chemical adhesion promoters.
Measurement of roughness on ultra-low-profile foil demanded special techniques. Traditional stylus-based contact methods were unsuitable because they could not detect the additional super-fine roughness brought about by ultra-flat nodular treatment. Non-contact interferometry was preferred, with results expressed in terms of “developed interfacial area ratio” (Sdr value), because this included both base the foil roughness and the nodular treatment roughness.
Mouzon demonstrated how the surface roughness of low-profile foils had been progressively reduced year-on-year since 2012, from a typical Sdr value of 8.9 for HVLP grade to a present-day value around 0.1 for HVLP5 grade, and showed corresponding graphs comparing insertion loss. She discussed the effects of metallic and non-metallic passivation treatments on signal integrity performance, etchability and thermal reliability, and pointed out that excellent peel strength could be maintained on PTFE material even after five hours at 150°C.
Next steps on the Circuit Foil roadmap for high speed digital and high frequency applications were to further reduce the foil roughness, to explore alternative passivation treatments and improved chemical adhesion promoters, and to optimize copper grain size and orientation.
The presentations of Manfred Huschka and Julie Mouzon provided an ideal background for EIPC board member Martyn Gaudion, managing director of Polar Instruments, to discuss the primary drivers for insertion loss on high-speed base material, and the tools with which they could be modelled.
He commented that PCB fabricators and designers were already familiar with the drivers for controlled-impedance traces on high-speed PCBs: trace width, height over substrate and base material dielectric constant, which set the conditions for signalling at frequencies below 2GHz. But when frequency rose far beyond that level, it was necessary to take additional physical properties into account. He made it clear that the drivers for loss were different from those for impedance, even though they acted on the same trace. And whereas characteristic impedance was independent of the length of the trace, insertion loss increased with length, so shorter interconnections were preferred. What caused losses? He identified the main factors and explained how the effects could be estimated and modelled. Although the drivers for impedance were still important, they had to be considered alongside the physical effects of copper conductivity, substrate dielectric loss and the impact of surface roughness on signal loss.
“Loss is the result of turning electrical power into heat.” Using a schematic cross-section of a coated microstrip, and taking care to avoid bewildering his audience with scientific over-complexity, he explained in basic terms the causes and effects of heating, both in the copper and in the dielectric, and skin effects as they related to roughness, even debating whether to build with rough-facing-rough or rough-facing-smooth in the stack-up. And the stack-up contained the information needed for modelling and predicting insertion loss characteristics. For calculating the effect of roughness Gaudion recommended the Cannonball-Huray modelling method as the most accurate. He believed that careful stack-up design could often avoid the need to use the more exotic materials, and that the ability to model loss characteristics before committing to actual manufacture was an opportunity to save on time and cost.
There was no shortage of requests for further information from the speakers as Paul Waldner took control and skilfully managed an energetic Q&A session before thanking all who had participated in another extremely successful EIPC Technical Snapshot event. The next is scheduled for April 14.