Just Ask Heidi: Eliminating EMC Failures

Reading time ( words)

First, we asked you to send in your questions for Happy Holden, Joe Fjelstad, Eric Camden, John Mitchell, and Tara Dunn in our “Just Ask” series. Now, it’s Heidi Barnes’s turn! Heidi is a senior signal and power integrity engineer at Keysight Technologies. She has written over 20 papers on SI and PI, and she is an active member in developing the new IEEE P370 standard involving interconnect S-parameter quality after fixture removal. Heidi has been awarded five patents and a NASA Silver Snoopy award (each Silver Snoopy pin flies on a space mission first), and she was named DesignCon's 2017 Engineer of the Year. We hope you enjoy “Just Ask Heidi.”

Q: We waste a lot of time with EMC failures. It’s constant. What are your thoughts on EMC?

A: Maybe it is too simple, but if one does a great SI design, then all the energy goes from Tx to Rx and there is no radiation. It’s the same with PI: if one does a great PI design, then all the energy goes into delivering power to the load and not feeding EMC resonances. The biggest culprit is often the layout of the return path, which is trivialized in schematics with a simple ground symbol that magically connects all grounds together. As EMC/EMI expert Dr. Bruce Archambeault is often heard saying, “Ground is a place for potatoes and carrots.”

In electronics, we have return current paths. Obviously, it is never that simple in engineering and one always needs to make trade-offs. I find that even the simplest of EM simulations can start to provide significant insights into ways of reducing potential EMC problems from resonances and crosstalk.

To submit your questions for Heidi, click here.



Suggested Items

Alternatives to Simulation

04/23/2021 | Dan Beeker, NXP Semiconductors
We are living in an age where the demands on electronic product designs are constantly evolving. The IC technology and operating speeds continue to pose significant challenges for teams as they work to develop their products. The increased transistor switching speeds and less forgiving compliance standards make signal integrity and electro-magnetic compliance more difficult to achieve. The status quo seems to have become, “We expect to fail EMC testing.”

Seven Tips for Your Next Stackup Design

02/01/2021 | Eric Bogatin, University of Colorado, Boulder
Rarely do we have the luxury of designing a board just for connectivity. When interconnects are not transparent, we must engineer them to reduce the noise they can generate. This is where design for signal integrity, power integrity and EMC—collectively high-speed digital engineering—are so important. Eric Bogatin offers seven tips for stackup design.

Just Ask Heidi Barnes: The Exclusive Compilation

01/15/2021 | I-Connect007 Editorial Team
We asked for your questions for Keysight Technologies' Heidi Barnes, and you took us up on it! We know you all enjoyed reading these questions and answers, so we’ve compiled all of them into one article for easy reference. We hope you enjoy having another bite at the apple.

Copyright © 2021 I-Connect007. All rights reserved.