Graphcore Leverages Multiple Mentor Technologies for its Massive, Second-generation AI Platform


Reading time ( words)

Graphcore has used a range of technologies from Mentor, a Siemens business, to successfully design and verify its latest M2000 platform based on the Graphcore Colossus™ GC200 Intelligence Processing Unit (IPU) processor.

Integrating 59.4 billion transistors on a single 823sqmm die and manufactured on TSMC’s 7nm processes, Graphcore’s second-generation IPU is one of the most complex processors ever made. To tackle this design challenge, Graphcore leveraged multiple Mentor solutions to handle a range of critical tasks including circuit verification, PCB design, protocol verification, thermal analysis, design-for-test (DFT) and bring-up of the state-of-the-art AI processor.

“Mentor’s extremely comprehensive portfolio of world-class IC and PCB design automation tools delivered the capacity, innovation, IP and trusted flows we needed for a design of this magnitude,” said Phil Horsfield, vice president of Silicon at Graphcore. “The performance and capacity of Mentor’s solutions allowed us to optimize the entire electronics system and focus on our differentiating IP, which helped us deliver a truly unique and compelling end-product.”

To deliver its second-generation IPU, Graphcore used Mentor tools including:

  • The industry-leading Calibre® platform, which includes Calibre nmDRC, the industry-leading physical verification solution, and Calibre nmLVS, the industry-leading circuit verification solution, both of which helped Graphcore support design intent for its second-generation device. Graphcore also used Calibre YieldEnhancer, featuring SmartFill, to control design planarity and help reduce turnaround time across multiple design iterations.
  • The Questa™ Verification IP solution for PCI Express 4.0, used to verify the Graphcore IPU’s PCIe Gen4, Ethernet and AMBA interconnect I/O busses. Questa technology provides a comprehensive verification solution for high-speed interconnects, and includes models, coverage, checkers, sequences, and test plans.
  • The Tessent™ software DFT platform, which helped Graphcore address a broad spectrum of DFT challenges associated with producing a device of the size and complexity of the Colossus GC200 IPU. Using Tessent SiliconInsight™ software for benchtop testing, Graphcore validated all onboard logic BIST, ATPG and memory BIST elements well ahead of schedule.
  • To develop the M2000 platform around the Colossus processors, Graphcore is leveraging Mentor solutions to address important power and thermal management challenges posed by such a dense design, enabling them to optimize performance and dramatically reduce design cycles. Graphcore designed the PCBs using Mentor’s Xpedition™ software concurrent team design platform, and verified the system for performance and manufacturability during the PCB design process with Mentor’s HyperLynx™ software DRC, Valor™ software NPI, and Simcenter™ Flotherm™ software.

“Demand for increasingly sophisticated AI chips is driving the industry’s top EDA software providers to enhance the capacity and scalability of their offerings across the entire design flow,” said Adrian Buckley, vice president, Europe for Mentor. “Customers like Graphcore are turning to Mentor’s highly advanced tools to help bring their products to market. Mentor is pleased to have played such a significant role in development of Graphcore’s ColossusGC200 IPU, which is one of the largest and most advanced AI platforms ever developed.”

Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world’s most successful electronic, semiconductor, and systems companies.  Corporate headquarters are located in Wilsonville, Oregon. Web site: http://www.mentor.com.

 

Share




Suggested Items

Rambus Driving a CXL Memory Option

06/30/2022 | Nolan Johnson, I-Connect007
In this interview with Arjun Bangre, director of product for high-speed interface IPs for PCI Express and CXL at Rambus, the discussion revolves around new developments in CXL, PCI Express, and interoperable IP solutions that Rambus has developed.

Pulsonix Collision Avoidance to Bring Mechanical Capabilities Into ECAD

05/19/2022 | I-Connect007 Editorial Team
The I-Connect Editorial Team recently spoke with Bob Williams, managing director of Pulsonix. He discussed some of the new features in the upcoming version of the Pulsonix PCB design tool, Version 12, including collision avoidance and other 3D options that allow certain MCAD functions within the ECAD environment.

A Textbook Look: Signal Integrity and Impedance

05/18/2022 | Pete Starkey, I-Connect007
Believing that I knew a bit about signal integrity and controlled impedance, I was pleased to take the opportunity to connect with an educational webinar that I hoped would extend my knowledge. In the event I was surprised at how little I actually knew, and the webinar was an excellent learning opportunity. The webinar was introduced and expertly moderated by Anna Brockman of Phoenix Contact in Germany.



Copyright © 2022 I-Connect007. All rights reserved.