# Book Excerpt: Power Integrity By Example, Chapter 5

The following is an excerpt from The Printed Circuit Designer's Guide to... Power Integrity by Example, written by Fadi Deek of Mentor, a Siemens Business. In this free eBook, Deek addresses problematic issues within electronic transmissions, and presents a variety of simulations and analyses in every chapter.

Chapter 5: Reducing Via-to-Via Coupling Using Capacitors

The peak noise shown in Figure 4.4 from a single rising-edge simulation was around 10 mV of noise with the aggressor switching up to 800 mV. This means the percentage of noise coupled from one via is 10/800 mV = 1.25%.

Coming from one aggressor via, this does not seem like a significant amount. However, in a printed circuit board, there are hundreds or even thousands of vias. This quickly becomes an important issue if a fraction of vias switch simultaneously.

In order to reduce the crosstalk level from all vias at once, the impedance of the cavity should be reduced. If the impedance is lowered, that means the voltage noise level propagating through the cavity is also lowered, because the two are directly proportional, as described by Ohm’s law.

Figure 5.1: Impedance profile, with 2-mil cavity in blue and 30-mil cavity in red.

Two methods to reduce cavity impedance are explored. One method is to reduce the cavity thickness from 30 mils to 2 mils. As shown in a previous section, the impedance dropped and the cavity was almost transparent.

It is always important to examine the cavity impedance profile to know what coupling and noise to expect. A comparison of the impedance profile with a 2-mil cavity versus a 30-mil cavity is plotted in Figure 5.1. The decrease in the cavity impedance shifted the LESL – Ccavity parallel resonance to around 16 MHz and the impedance dropped, too.

Figure 5.2: Via-to-via coupling, with 2-mil cavity in blue and 30-mil cavity in red.

Based on this, the noise injected into the cavity should be reduced and the period of the ringing should be longer than before at 62 ns. A simulation was run to measure the crosstalk between the vias and is plotted in Figure 5.2. The peak crosstalk is now measured on the blue plot a little bit higher than 1.2 mV. This is a significant decrease with just one simple change—the noise level percentage dropped to 0.1% for the 2-mil cavity from 1.25% for the 30-mil cavity.

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## I-Connect007 Editor’s Choice: Five Must-Reads for the Week

08/14/2020 | Andy Shaughnessy, Design007 Magazine
This week’s picks include a little of everything. We have an interview with the founder of Avishtech, a new EDA software company that has a spin on field solvers and stackup tools. We also have an interview with Mike Carano, who discusses the need for mentors. Then, there’s news about partnership between Koh Young and Mentor, and an iNEMI "best practices" guide for disinfecting your facility. Finally, we've compiled all of the "Just Ask Happy" entries into a single document for your viewing pleasure. Happy Friday!

## Avishtech: A New Player in the Field Solver and PCB Simulation Tools Market

08/13/2020 | I-Connect007 Editorial Team
It has been a crazy year with lots of ups and downs. But within the clouds, we’ve seen plenty of silver linings, too. Case in point: Avishtech, a brand-new company lead by founder and CEO Keshav Amla. (You may be familiar with his father, Tarun Amla, a veteran PCB materials technologist who is now with ITEQ.) We recently caught up with Keshav and asked him to discuss his company’s simulation tools, his plans for the company, and what it’s like launching a company in this “new normal.”