Mentor Webinar: Ensuring DDR4 Electrical Performance at Intended Data Rates


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DDR interfaces have many signal integrity and timing requirements that must be guaranteed between multiple signal groups. Conformance to the requirements should be verified before a board is fabricated to reduce the chance of prototype spins. Traditionally, designers have relied on dedicated SI experts to perform this task, or laid out boards based on manufacturer’s guidelines and skipped post-route verification entirely, hoping to avoid problems in the lab. Increasing data rates have pushed DDR operating margins to the point where simply following physical design rules is no longer enough to ensure that a design will work as intended.

This on-demand webinar will discuss the different electrical requirements associated with DDR designs and show how board and system designers can use HyperLynx to perform post-route verification themselves, helping free up scarce SI experts to focus on their company’s most challenging analysis problems.

The webinar is presented by Min Maung, a senior technical marketing engineer for HyperLynx Analysis Tools Suite for the Electronic Board Systems segment at Mentor, a Siemens Business.

To view this on-demand webinar, or for more information, click here.

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