Cadence Expands Design IP Portfolio with 56G Long-Reach PAM4 SerDes


Reading time ( words)

Cadence Design Systems, Inc. recently announced the availability of 56G long-reach SerDes IP on TSMC’s N7 and N6 process technologies. 

Hyperscale computing continues to be the main driver for very high-speed SerDes, and 112G/56G is a key enabler for cloud data center and optical networking applications. 56G connectivity is particularly important for 5G infrastructure deployment, both in baseband and remote radio head systems. To address this broader market, Cadence has expanded its PAM4 SerDes portfolio with 56G long-reach SerDes IP on the TSMC N7 and N6 processes delivering optimized power, performance and area (PPA). For more information on the 56G long-reach PAM4 SerDes, please visit www.cadence.com/go/56GSerDes.

Cadence is ready to engage with customers immediately on 5G, compute server processor and machine learning workload-accelerator system-on-chip (SoC) design enablement. The Cadence® 56G long-reach SerDes IP delivers design excellence in support of the Cadence Intelligent System Design strategy, offering designers a number of benefits, including:

  • Best-in-class 36db+ insertion loss using Cadence’s well-proven multi-rate DSP technology
  • Industrial temperature rangeCPRI data rate support and per-lane PLL are ideal for 5G applications
  • 56G long-reach performance has been achieved on N7 test silicon and is compatible with the N6 process
  • Fully compliant with the IEEE standard specification
  • Programmable power configurations via a unique firmware-controlled adaptive power optimizer, which provides optimal power and performance tradeoffs and more efficient system designs based on platform requirements
  • Optimal data recovery through the programmable DSP-based architecture, which allows optimal power delivery for a given reach and provides superior data recovery under lossy and noisy channel conditions
  • Improved flexibility enabled by the extended reach capability lets customers use lower cost PCBs and achieve greater flexibility in PCB and system design

“We are pleased to see Cadence expand its PAM4 offerings to include 56G and extend support to TSMC N7 and N6 process technologies,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “This joint effort combining Cadence’s leading edge SerDes IP and TSMC’s advanced process technologies will help our customers unleash their silicon innovations for emerging 5G and hyperscale data center applications.”

“After being first to market in 2019 with silicon-proven 112G-LR SerDes on TSMC 7nm technology, we have now expanded our offering to include PPA-optimized 56G-LR to address the connectivity needs of the 5G infrastructure and AI/ML market. This new PAM4-based 56G-LR SerDes is based on Cadence’s well-proven multi-rate DSP technology,” said Rishi Chugh, vice president of product marketing, IP Group at Cadence. “The availability of Cadence’s 56G long-reach SerDes IP on the TSMC N7 and N6 processes accelerates the adoption and deployment of cost-effective 100G and 400G networks.”

Share

Print


Suggested Items

Stephen Chavez and Happy Holden on Designing Reliable Vias

12/02/2020 | I-Connect007 Editorial Team
Andy Shaughnessy and Happy Holden speak with Stephen Chavez, a staff engineer with an aerospace company and chairman of the Printed Circuit Engineering Association (PCEA), about designing vias for greater reliability. They also address several areas where they can look to improve reliability, a variety of steps that designers should take to help ensure more robust vias, and some testing and educational resources that PCB designers and design engineers should be aware of.

This Month in Design007 Magazine: HDI Design, Landless Vias, VeCS, and More

11/09/2020 | I-Connect007 Editorial Team
Andy Shaughnessy, Happy Holden, and Dan Feinberg recently met with James Hofer, general manager of Accurate Circuit Engineering, to discuss via design techniques and via reliability from the fabricator’s viewpoint. As Hofer explained, even with open lines of communication between the designer and the board shop, there are plenty of variables to contend with regarding proper via design, especially when working with PTFE materials.

Roundtable Discussion: App Notes and Fab Notes

11/09/2020 | Andy Shaughnessy, Design007 Magazine
Andy Shaughnessy recently invited four recent contributors—Dana Korf, Jen Kolar, Mark Thompson, and Kelly Dack—to review the June and August 2020 issues of Design007 Magazine, which covered app notes and fab notes, respectively. In this wide-ranging roundtable, the group discusses some of the ongoing challenges related to incomplete and inaccurate design data and why communication can preclude many of these problems. What follows is the transcript from this conversation.



Copyright © 2020 I-Connect007. All rights reserved.