Mentor Webinar May 5: Ensuring DDR4 Performance at Intended Data Rate


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DDR interfaces have many signal integrity and timing requirements that need to be guaranteed between multiple signal groups. Conformance to the requirements should be verified before a board is fabricated to reduce the chance of prototype spins. Traditionally, designers have relied on dedicated SI experts to perform this task or laid out boards based on manufacturer’s guidelines and skipped post-route verification entirely, hoping to avoid problems in the lab. Increasing data rates have pushed DDR operating margins to the point where simply following physical design rules is no longer enough to ensure that a design will work as intended.

This webinar by Mentor, a Siemens business, will be held twice on May 5, 2020: from 2-3 PM London time (UTC+1), and 2-3 PM Eastern time in the US. Presenter Min Maung will discuss the different electrical requirements associated with DDR designs and show how board and system designers can use HyperLynx to perform post-route verification themselves, helping free up scarce SI experts to focus on their company’s most challenging analysis problems.  

What Attendees Will Learn

  • DDR electrical requirements for signal integrity and timing
  • Why “routing by the rules” isn’t enough anymore
  • Why JEDEC specifications only give you half of the information you need
  • How controller/DRAM configuration affects routing requirements
  • How to use HyperLynx post-route verification to optimize margins for designs as routed

Who Should Attend

  • PCB/system designers
  • Engineering managers
  • Signal integrity specialists
  • PCB layout designers

To register for this web seminar, click here.

 

 

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