Mentor Webinar May 5: Ensuring DDR4 Performance at Intended Data Rate


Reading time ( words)

DDR interfaces have many signal integrity and timing requirements that need to be guaranteed between multiple signal groups. Conformance to the requirements should be verified before a board is fabricated to reduce the chance of prototype spins. Traditionally, designers have relied on dedicated SI experts to perform this task or laid out boards based on manufacturer’s guidelines and skipped post-route verification entirely, hoping to avoid problems in the lab. Increasing data rates have pushed DDR operating margins to the point where simply following physical design rules is no longer enough to ensure that a design will work as intended.

This webinar by Mentor, a Siemens business, will be held twice on May 5, 2020: from 2-3 PM London time (UTC+1), and 2-3 PM Eastern time in the US. Presenter Min Maung will discuss the different electrical requirements associated with DDR designs and show how board and system designers can use HyperLynx to perform post-route verification themselves, helping free up scarce SI experts to focus on their company’s most challenging analysis problems.  

What Attendees Will Learn

  • DDR electrical requirements for signal integrity and timing
  • Why “routing by the rules” isn’t enough anymore
  • Why JEDEC specifications only give you half of the information you need
  • How controller/DRAM configuration affects routing requirements
  • How to use HyperLynx post-route verification to optimize margins for designs as routed

Who Should Attend

  • PCB/system designers
  • Engineering managers
  • Signal integrity specialists
  • PCB layout designers

To register for this web seminar, click here.

 

 

Share




Suggested Items

The Test Connection: Spreading the Word About DFT

12/07/2022 | Andy Shaughnessy, PCB Design007
As signal speeds continue to increase and feature sizes decrease, PCB designers are beginning to pay greater attention to test and design for test (DFT) strategies. Bert Horner, president of The Test Connection in Hunt Valley, Maryland, is spearheading this drive to show designers the benefits of a solid DFT plan, as well as the downside of not having a test strategy. I met with Bert at PCB Carolina, where he was exhibiting and presenting a paper during the conference. We discussed his presentation, as well as why designers need to understand test and DFT issues, and why we need to see the PCB as one small—but very important—part of the entire system.

DownStream Flexes in Rigid-Flex

11/14/2022 | Andy Shaughnessy, Design007 Magazine
During PCB West, I caught up with DownStream Technologies co-founder Joe Clark and Senior Product Marketing Manager Mark Gallant. We discussed some of their latest tool updates, including a greater focus on bringing post-processing functionality, such as inter-layer analysis capability, to rigid-flex circuits. Joe also offered a look at global design trends going into 2023, as more engineers take on PCB designer roles while senior designers are retiring.

Sunstone’s Matt Stevenson Shares Insights From New PCB Design Book

10/27/2022 | Nolan Johnson, I-Connect007
There’s designing the “perfect” circuit board and then there’s designing a board that is “perfect for manufacturing.” While seasoned designers and design engineers understand many of the nuances, PCB fabricator Sunstone Circuits has just published a new book specifically for new designers who have the knowledge of design but are still learning what it means to get the board manufactured. Sunstone’s Matt Stevenson takes the reader through a series of situations that should help clarify what’s happening in the fabrication process and how to adjust a board design to be better suited for manufacturing.



Copyright © 2022 I-Connect007 | IPC Publishing Group Inc. All rights reserved.