Register Now for Zuken’s DDR5 Webinar on Nov. 13


Reading time ( words)

This webinar will explore a predictive, productive and insightful workflow to get to an optimal DDR5 design that performs to the target speed grade, reliably. 

DDR5 is the latest generation of memory in development, doubling the peak data rate to 6400 MT/s (compared to DDR4). With great technical ambitions come much tighter specifications for system PCB designers, especially when faced with channel loss, skew, reflections and crosstalk, all of which become much more significant at higher frequencies. In fact, PCB design margins are so minimal that DDR5 introduces equalization on the commodity DRAM chips for the first time.

The presentation will begin with pre-layout simulation to explore design choices, then transition to constraint-based high-speed routing in Zuken CR-8000. The design will then be verified by electromagnetic simulation and system simulations in order to build confidence in the final DDR5 design.

Date/Time

November 13, 2 PM EST

Registration

To register for this event, or for more information, click here.

Share

Print


Suggested Items

Bridging the Simulation Tool Divide

04/12/2021 | I-Connect007 Editorial Team
Todd Westerhoff of Siemens EDA recently spoke with the I-Connect007 Editorial Team about the divide between users of high-powered enterprise simulation tools and those who need a more practical tool for everyday use, and how Siemens is working to bridge the gap. Todd also shared his views on why so many engineers do not use simulation, as well as advice for engineers just getting started with simulation tools.

Barry Olney’s High-Speed Simulation Primer

04/09/2021 | Barry Olney, In-Circuit Design Pty Ltd
The I-Connect007 editorial team recently spoke with Barry Olney of iCD about simulation. Barry, a columnist for Design007 Magazine, explains why simulation tools can have such a steep learning curve, and why many design engineers are still not using simulation on complex high-speed designs.

Eliminating ‘Garbage In, Garbage Out’ With Checks and Balances

03/26/2021 | Nick Barbin, Optimum Design Associates
The proverbial saying “garbage in, garbage out” holds true in the electronic product development world. PCB designers stand squarely in the middle of a busy information intersection flowing with inputs and outputs. Missing or bad information at the beginning of a design project will undoubtedly lead to board re-spins, increased costs, and most importantly, a delayed product release. The same can be said about the PCB designer who doesn’t provide a fully checked and comprehensive data package to the downstream manufacturers, i.e., “throwing it over the fence.”



Copyright © 2021 I-Connect007. All rights reserved.