Robert Hanson to Present at Cascade DC Chapter Meeting Sept. 18

Reading time ( words)

Be sure to sign up for the upcoming IPC Designers Council Cascade Chapter seminar on September 18, 2019 at Lake Washington Institute of Technology. Americom Seminars President Robert Hanson, a veteran high-speed design instructor, will present "Differential Signaling: Tradeoffs for Optimization of Signal Quality and Routing.” This evening event is free and dinner will be provided, courtesy of Cadence Design Systems. Don't miss out on this great educational opportunity to advance your knowledge and design skills.

During this seminar, attendees will learn about the attributes of loosely/tightly coupled differential pairs, as well as definitions and examples of differential-mode and common-mode voltage, current and differential impedance, both odd and even modes. The advantages and disadvantages of edge (side-by-side), broadside (dual), asymmetric and microstrip differentials will also be discussed.

Pertinent topics regarding reflections and crosstalk in differentials will be included. Metastability, clock skew, driver skew, bit pattern sensitivity, ISI, skin effect, dielectric constant, jitter, BER, and the eye diagram are part of the session. Other topics that will be discussed include matching electrical lengths, differential unbalance, controlling Z_o, differential/common mode radiation, transversing connectors, and other signal quality issues and design guides.

Attendees will learn: 

• All voltage, impedance, and current definitions for differential signaling.
• Comparison of edge, broadside, asymmetric, and microstrip differential layouts and effectiveness in controlling crosstalk and radiated emissions.
• How to overcome differential unbalance.
• How to control Z_o when switching from loosely coupled to tightly coupled (and vice versa) differential layouts.
• The major drawback when using broadside differentials.
• Why differential signaling is essential for long haul, high-speed transmission lines.

To sign up, please go to our website: http://cascade-ipcdc.org

Meeting Agenda

5:45 pm to 6:00 pm: Dinner is served
6:00 pm to 8:30 pm: Presentation
8:30 pm to 8:40 pm: Q&A
8:40 pm to 8:45 pm: Door prize drawings

Next Chapter meeting: December 4, 2019

Tim Mullin, President
IPC Designers Council - Cascade Chapter
http://cascade-ipcdc.org
Cell: (253) 229-6914

 

09/19/2019 | Rebecca Lord and John McMillan, Mentor, a Siemens business

PCB designs commonly undergo multiple respins as a result of inconspicuous signal integrity (SI), power integrity (PI), and electromagnetic interference (EMI) violations. At an average cost of nearly $28,000 per respin, ensuring that a given design meets its performance, time to market, and cost goals is imperative. To help eliminate complicated and difficult-to-diagnose layout violations, some PCB tool suites offer unique electrical design rule checks (DRC).

09/16/2019 | I-Connect007 Research Team

In a recent survey, we asked the following question: What feature would you like to see in your CAD tool? Here are a few of the answers, edited slightly for clarity.

09/12/2019 | Barry Matties, Publisher, I-Connect007

During a recent trip to the U.K., Barry Matties spoke with Bob Williams, the managing director of Pulsonix, about training the new generation of designers. He explained how the company reaches out to local high schools, colleges, universities, and user groups to advocate for careers in PCB design and manufacturing.