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This article will discuss the effect of decoupling capacitors upon a PCB’s power and signal integrity. The study was performed with post-layout co-simulation of power and signal integrity to analyze power distribution network impedance, simultaneous switching noise, and eye diagrams.
It is crucial for hardware designers to identify the resonant frequency of each element (e.g., bypass/decoupling capacitor, planar capacitance, and interconnect inductance) of the power distribution network (PDN) on a PCB and its impact on power integrity. A PCB with poor power integrity—such as a higher-than-targeted PDN impedance across the wideband range—results in simultaneous switching noise (SSN) and a shrunken eye diagram of the signal transmitted by the IC that draws power from the PDN. This article demonstrates the post-layout co-simulation of power and signal integrity using Mentor HyperLynx to analyze the impact of decoupling capacitors upon PDN impedance, SSN, and eye diagrams.
Analysis and Results
A PCB containing a system-on-a-chip (SoC) with DDR4 memory interface is laid out. In Figure 1a, the PDN named 1.2V on layer 4 supplies power to a memory interface that consists of one memory IC highlighted in blue. Meanwhile, the ground or reference plane, highlighted in green, is laid out on layer 5. The memory IC has 13 BGA power pins. The footprint of the 0.22-uF decoupling capacitor (highlighted in brown) in a 0201 package dimension is placed across each of the power pins and the ground. Additionally, the footprint of bypass capacitors, 10 uF and a 1 uF respectively (highlighted in brown as well), is placed across the 1.2V power net and ground. The eight data signals of this memory interface are shown in Figure 1b.
To view the rest of this article, which appeared in the August 2019 issue of Design007 Magazine, click here.
I-Connect007 Editorial Team
I recently spoke with Todd Westerhoff, product marketing manager for signal integrity software tools at Siemens. We discussed a new capability called HyperLynx Apps that offers a new take on traditional signal and power integrity analysis, and how that fits in with the Siemens plan to put SI and PI tools into the hands of more designers early in the design cycle.
Heidi Barnes, Keysight Technologies
Electromagnetic (EM) solvers based on Maxwell’s equations have proven invaluable in the advancement of digital electronics and wireline communications. Plain and simple, electrical engineers need to know what a circuit or electrical interconnect will do when excited by a dynamic or varying signal. In the signal integrity world, an interconnect that passes a DC connectivity check can completely fail at higher frequencies. In the power integrity world, a power rail that measures the correct DC voltage could easily go into oscillation when a dynamic load is applied. Learning the basic skills to fire up an EM simulator, obtain qualitative answers in minutes, and higher fidelity answers in a few days, can be the difference between sleepless nights of product failures vs. robust designs with wide design margins.
Andy Shaughnessy, Design007 Magazine
Electrical and mechanical engineers may be working on the same product development teams, but they speak different languages, and they have completely different objectives. As a result, these folks almost never use the same software tools.
But Cadence’s new Celsius Thermal Solver is an exception to the rule. In a new CadenceTECHTALK webinar, “How Static and Dynamic IR Drop Analysis Can Help PCB Designs and Challenges,” product manager Melika Roshandell and SerDes SI/PI engineer Karthik Mahesh Rao explain how the EE and ME can both use the Celsius Thermal Solver to achieve their disparate objectives.