Calculation of Frequency-Dependent Effective Roughness Dielectric Parameters for Copper Foil Using Equivalent Capacitance Models


Reading time ( words)

Printed circuit boards (PCBs) used in high-speed digital design are known to have a substantial level of copper foil roughness which compromises signal integrity (SI) and may also cause electromagnetic compatibility (EMC) problems. Therefore, knowledge of the correct parameters of laminate PCB dielectrics refined from any copper foil roughness impact and the proper foil roughness characterization are important constituents of modeling high-speed digital electronics designs, see, e.g., [1,2,3] and references therein.

The Effective Roughness Dielectric (ERD) concept was introduced in [4,5,6]. ERD is a homogeneous lossy dielectric layer of certain thickness Tr with effective (averaged) dielectric constant DKr and dissipation factor DFr. ERD is placed on a smooth conductor surface to substitute an inhomogeneous transition layer between a conductor and laminate substrate dielectric. While the concept is simple, it is physically illuminating, meaningful, and powerful. It has been successfully applied to model conductor (copper foil) roughness in printed circuit boards for signal integrity (SI) and electromagnetic interference (EMI) purposes when designing high-speed digital electronics devices [7,8]. The ERD model has been implemented and tested in a number of numerical electromagnetic modeling tools, see, e.g., [9,10,11,12].

In our previous publications [6,13,14], the ERD “design curves”, determining the ranges of the DKr and DFr parameters for different types of PCB copper foils, were developed. The methodology of generating these “design curves” is based on the following procedures:

  • Stripline S-parameter Sweep (S3) technique to measure S-parameters of single-ended comparatively long (~40 cm, or 16 inches) striplines with TRL calibration to remove connector effects [15,16]; 
  • Scanning Electron Microscopy (SEM) or high-resolution optical microscopy of cross-sections of PCB samples with signal traces and the proper quantification of surface roughness profile parameters [17,18,19];
  • Differential Extrapolation Roughness Measurement (DERM) technique [20,21,22]; and
  • 2D-FEM and/or 3D FIT numerical modeling that allow for accurately fitting the measured S-parameters of the striplines and extract the data for DKr and DFr of the roughness layers [4,6,13,14]. This fitting may include an optimization procedure, e.g., a genetic algorithm, to minimize the discrepancy between the modeled and measured S-parameters.

The "design curves" in the abovementioned papers were generated using SEM and/or optical microscopy to quantify foil roughness. Any designer can use these “design curves” and does not necessarily need to cut a PCB and prepare samples of the lines cross-sections for microscopic inspection. It is sufficient to know which type of foil is used in the PCB under test – this may be standard (STD) foil, VLP (very low profile), RTF (reverse-treated foil), or HVLP (hyper-very low profile)/ SVLP (super-very low profile) foil. Each foil type (group) has some ranges of DKr, DFr, and Tr values, and a designer may take average values DKr, DFr, and Tr within these ranges for the reasonable estimation of the data which then could be used in modeling of the PCB designs.

Although the “design curves” were developed using fitting between the experimental data and modeling results, it is always desirable to have an analytical model. In this work, the DKr and DFr parameters are derived based on the understanding that the transition layer between the dielectric and foil contains gradual variation of concentration of metallic inclusions: from zero concentration in laminate dielectric through some percolation limit to 100% at the smooth copper foil level. The equivalent material parameters of this layered structure can be obtained using equivalent capacitance approach. In the equivalent capacitor the dielectric properties vary gradually according to the concentration profile of metallic particles in the roughness layer. The concentration profile can be obtained from SEM or high-resolution optical microscopy. As concentration of metallic particles increases along the axis normal to the laminate dielectric and foil boundary, two regions can be determined: insulating (pre-percolation) and conducting (percolation). Rates of increase of effective loss (or effective conductivity) in these two regions significantly differ. The proposed model of equivalent capacitance with gradient dielectric has been applied to STD and VLP foils, and the results are validated using 3D numerical electromagnetic simulations.

Description of Equivalent Capacitance Model

A roughness profile on a PCB conductor surface can be tested using optical or SEM microscopy, or a surface profiler. The average contents (volume concentration) of metallic particles in the roughness layer varies as a function of the coordinate z normal to the surface. It can be approximated by an exponential function,

Martina-EQ1.JPG     (1)

where a and K1 are the fitting parameters.

Two separate regions of effective roughness dielectric can be considered:

Region I:  0p, where the concentration of metallic inclusions is below the percolation threshold, i.e., where the mixture remains in the dielectric phase; this is the region adjacent to the dielectric matrix of the PCB. Herein, Tp is the distance within the layer at which percolation is reached.

Region II: Tp, where the concentration of metallic inclusions is higher than the percolation threshold; this is the region adjacent to the smooth foil level and is conducting. Herein, T is the entire thickness of ERD layer. It includes,

Martina-EQ2.JPG     

(2)

where ΔT is the thickness of the region above the percolation.

The concentration , at which percolation will occur for the metallic particles in the roughness dielectric layer, can be obtained empirically, i.e., estimated from the microscopy pictures, or from the profiler data. By solving the equation,

Martina-EQ4.JPG     

(3)

with respect to Tp, one can get the height of the dielectric phase of ERD.

First, let us consider the region 0p. This is the dielectric layer with relative permittivity varying according to the profile function (1) from the matrix dielectric properties em (at z=0) to the final pre-percolation value ep (at z=Tp). Since dielectric function varies with z as,

Martina-EQ4.JPG     

(4)

The effective permittivity of such a layer can be calculated through the equivalent partial layered capacitor consisting of series connection of sublayer capacitors. The capacitance of the resultant capacitor with variable properties of the dielectric is,

Martina-EQ5.JPG     

(5)

where Cis the capacitance of the corresponding air-filled rectangular parallel-plate capacitor of thickness, d. Herein, d = Tp.

The effective dielectric properties of such dielectric layer can be easily derived from (5) as

Martina-EQ6.JPG     

(6)

Share

Print


Suggested Items

AltiumLive Munich: Day 1 Keynotes

01/28/2019 | Pete Starkey, I-Connect007
The weather forecast was wrong! Despite my apprehension and winter clothes, there was very little snow at the Hilton Munich Airport. It could have been any season of the year inside the splendid convention facility, which was also the venue for the second European AltiumLive design summit. AltiumLive brought together a family of over 220 electronics engineers and designers eager to learn from top industry experts and applications specialists who were equally eager to share their knowledge and experience freely.

The Quest for Perfect Design Data Packages

01/18/2019 | Barry Matties, I-Connect007
There’s an ongoing problem in the PCB industry: fabrication shops are receiving incomplete or inadequate design data packages, leaving manufacturers scrambling to fill in the blanks. For a quick-turn prototype shop like Washington-based Prototron, with over 5,000 customers and up to 60% of orders coming from new customers each month, that can add up to a lot of wasted time and effort just in the quoting stage. Dave Ryder, Prototron president, and Mark Thompson, engineering support, delve into this continuing issue and more.

A Fractal Conversation with Jim Howard and Greg Lucas

01/15/2019 | Barry Matties and Andy Shaughnessy, I-Connect007
Veteran PCB technologists Jim Howard and Greg Lucas have made an interesting discovery: Certain shapes of copper planes make a PCB run more efficiently than other shapes, a process they dubbed fractal design. It doesn’t appear to cost a penny more, and testing suggests that fractal design techniques could eliminate edge noise. Barry Matties and Andy Shaughnessy asked Jim and Greg to discuss the fractal design process, and the advantages of using this technique.



Copyright © 2019 I-Connect007. All rights reserved.