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Printed circuit boards (PCBs) used in high-speed digital design are known to have a substantial level of copper foil roughness which compromises signal integrity (SI) and may also cause electromagnetic compatibility (EMC) problems. Therefore, knowledge of the correct parameters of laminate PCB dielectrics refined from any copper foil roughness impact and the proper foil roughness characterization are important constituents of modeling high-speed digital electronics designs, see, e.g., [1,2,3] and references therein.

The Effective Roughness Dielectric (ERD) concept was introduced in [4,5,6]. ERD is a homogeneous lossy dielectric layer of certain thickness T_{r} with effective (averaged) dielectric constant DK_{r} and dissipation factor DF_{r}. ERD is placed on a smooth conductor surface to substitute an inhomogeneous transition layer between a conductor and laminate substrate dielectric. While the concept is simple, it is physically illuminating, meaningful, and powerful. It has been successfully applied to model conductor (copper foil) roughness in printed circuit boards for signal integrity (SI) and electromagnetic interference (EMI) purposes when designing high-speed digital electronics devices [7,8]. The ERD model has been implemented and tested in a number of numerical electromagnetic modeling tools, see, *e.g.*, [9,10,11,12].

In our previous publications [6,13,14], the ERD “design curves”, determining the ranges of the DK_{r} and DF_{r} parameters for different types of PCB copper foils, were developed. The methodology of generating these “design curves” is based on the following procedures:

- Stripline S-parameter Sweep (S3) technique to measure S-parameters of single-ended comparatively long (~40 cm, or 16 inches) striplines with TRL calibration to remove connector effects [15,16];
- Scanning Electron Microscopy (SEM) or high-resolution optical microscopy of cross-sections of PCB samples with signal traces and the proper quantification of surface roughness profile parameters [17,18,19];
- Differential Extrapolation Roughness Measurement (DERM) technique [20,21,22]; and
- 2D-FEM and/or 3D FIT numerical modeling that allow for accurately fitting the measured S-parameters of the striplines and extract the data for DK
_{r}and DF_{r}of the roughness layers [4,6,13,14]. This fitting may include an optimization procedure,*e.g.*, a genetic algorithm, to minimize the discrepancy between the modeled and measured S-parameters.

The "design curves" in the abovementioned papers were generated using SEM and/or optical microscopy to quantify foil roughness. Any designer can use these “design curves” and does not necessarily need to cut a PCB and prepare samples of the lines cross-sections for microscopic inspection. It is sufficient to know which type of foil is used in the PCB under test – this may be standard (STD) foil, VLP (very low profile), RTF (reverse-treated foil), or HVLP (hyper-very low profile)/ SVLP (super-very low profile) foil. Each foil type (group) has some ranges of DK_{r}, DF_{r}, and T_{r} values, and a designer may take average values DK_{r}, DF_{r}, and T_{r} within these ranges for the reasonable estimation of the data which then could be used in modeling of the PCB designs.

Although the “design curves” were developed using fitting between the experimental data and modeling results, it is always desirable to have an analytical model. In this work, the DK_{r} and DF_{r} parameters are derived based on the understanding that the transition layer between the dielectric and foil contains gradual variation of concentration of metallic inclusions: from zero concentration in laminate dielectric through some percolation limit to 100% at the smooth copper foil level. The equivalent material parameters of this layered structure can be obtained using equivalent capacitance approach. In the equivalent capacitor the dielectric properties vary gradually according to the concentration profile of metallic particles in the roughness layer. The concentration profile can be obtained from SEM or high-resolution optical microscopy. As concentration of metallic particles increases along the axis normal to the laminate dielectric and foil boundary, two regions can be determined: insulating (pre-percolation) and conducting (percolation). Rates of increase of effective loss (or effective conductivity) in these two regions significantly differ. The proposed model of equivalent capacitance with gradient dielectric has been applied to STD and VLP foils, and the results are validated using 3D numerical electromagnetic simulations.

**Description of Equivalent Capacitance Model**

A roughness profile on a PCB conductor surface can be tested using optical or SEM microscopy, or a surface profiler. The average contents (volume concentration) of metallic particles in the roughness layer varies as a function of the coordinate *z* normal to the surface. It can be approximated by an exponential function,

(1)

where *a* and *K _{1}* are the fitting parameters.

Two separate regions of effective roughness dielectric can be considered:

*Region I:**0p*, where the concentration of metallic inclusions is below the percolation threshold, *i.e.*, where the mixture remains in the dielectric phase; this is the region adjacent to the dielectric matrix of the PCB. Herein, *T _{p}* is the distance within the layer at which percolation is reached.

*Region II:**T _{p}, where the concentration of metallic inclusions is higher than the percolation threshold; this is the region adjacent to the smooth foil level and is conducting. Herein, T is the entire thickness of ERD layer. It includes,*

(2)

where ΔT is the thickness of the region above the percolation.

The concentration , at which percolation will occur for the metallic particles in the roughness dielectric layer, can be obtained empirically, *i.e.*, estimated from the microscopy pictures, or from the profiler data. By solving the equation,

(3)

with respect to *T _{p}*, one can get the height of the dielectric phase of ERD.

First, let us consider the region *0p*. This is the dielectric layer with relative permittivity varying according to the profile function (1) from the matrix dielectric properties *e _{m}* (at z=0) to the final pre-percolation value

*e*(at

_{p}*z*=

*T*). Since dielectric function varies with

_{p}*z*as,

(4)

The effective permittivity of such a layer can be calculated through the equivalent partial layered capacitor consisting of series connection of sublayer capacitors. The capacitance of the resultant capacitor with variable properties of the dielectric is,

(5)

where *C _{0 }*is the capacitance of the corresponding air-filled rectangular parallel-plate capacitor of thickness,

*d*. Herein, d = T

_{p}.

The effective dielectric properties of such dielectric layer can be easily derived from (5) as

(6)