Calculation of Frequency-Dependent Effective Roughness Dielectric Parameters for Copper Foil Using Equivalent Capacitance Models
Printed circuit boards (PCBs) used in high-speed digital design are known to have a substantial level of copper foil roughness which compromises signal integrity (SI) and may also cause electromagnetic compatibility (EMC) problems. Therefore, knowledge of the correct parameters of laminate PCB dielectrics refined from any copper foil roughness impact and the proper foil roughness characterization are important constituents of modeling high-speed digital electronics designs, see, e.g., [1,2,3] and references therein.
The Effective Roughness Dielectric (ERD) concept was introduced in [4,5,6]. ERD is a homogeneous lossy dielectric layer of certain thickness Tr with effective (averaged) dielectric constant DKr and dissipation factor DFr. ERD is placed on a smooth conductor surface to substitute an inhomogeneous transition layer between a conductor and laminate substrate dielectric. While the concept is simple, it is physically illuminating, meaningful, and powerful. It has been successfully applied to model conductor (copper foil) roughness in printed circuit boards for signal integrity (SI) and electromagnetic interference (EMI) purposes when designing high-speed digital electronics devices [7,8]. The ERD model has been implemented and tested in a number of numerical electromagnetic modeling tools, see, e.g., [9,10,11,12].
In our previous publications [6,13,14], the ERD “design curves”, determining the ranges of the DKr and DFr parameters for different types of PCB copper foils, were developed. The methodology of generating these “design curves” is based on the following procedures:
- Stripline S-parameter Sweep (S3) technique to measure S-parameters of single-ended comparatively long (~40 cm, or 16 inches) striplines with TRL calibration to remove connector effects [15,16];
- Scanning Electron Microscopy (SEM) or high-resolution optical microscopy of cross-sections of PCB samples with signal traces and the proper quantification of surface roughness profile parameters [17,18,19];
- Differential Extrapolation Roughness Measurement (DERM) technique [20,21,22]; and
- 2D-FEM and/or 3D FIT numerical modeling that allow for accurately fitting the measured S-parameters of the striplines and extract the data for DKr and DFr of the roughness layers [4,6,13,14]. This fitting may include an optimization procedure, e.g., a genetic algorithm, to minimize the discrepancy between the modeled and measured S-parameters.
The "design curves" in the abovementioned papers were generated using SEM and/or optical microscopy to quantify foil roughness. Any designer can use these “design curves” and does not necessarily need to cut a PCB and prepare samples of the lines cross-sections for microscopic inspection. It is sufficient to know which type of foil is used in the PCB under test – this may be standard (STD) foil, VLP (very low profile), RTF (reverse-treated foil), or HVLP (hyper-very low profile)/ SVLP (super-very low profile) foil. Each foil type (group) has some ranges of DKr, DFr, and Tr values, and a designer may take average values DKr, DFr, and Tr within these ranges for the reasonable estimation of the data which then could be used in modeling of the PCB designs.
Although the “design curves” were developed using fitting between the experimental data and modeling results, it is always desirable to have an analytical model. In this work, the DKr and DFr parameters are derived based on the understanding that the transition layer between the dielectric and foil contains gradual variation of concentration of metallic inclusions: from zero concentration in laminate dielectric through some percolation limit to 100% at the smooth copper foil level. The equivalent material parameters of this layered structure can be obtained using equivalent capacitance approach. In the equivalent capacitor the dielectric properties vary gradually according to the concentration profile of metallic particles in the roughness layer. The concentration profile can be obtained from SEM or high-resolution optical microscopy. As concentration of metallic particles increases along the axis normal to the laminate dielectric and foil boundary, two regions can be determined: insulating (pre-percolation) and conducting (percolation). Rates of increase of effective loss (or effective conductivity) in these two regions significantly differ. The proposed model of equivalent capacitance with gradient dielectric has been applied to STD and VLP foils, and the results are validated using 3D numerical electromagnetic simulations.
Description of Equivalent Capacitance Model
A roughness profile on a PCB conductor surface can be tested using optical or SEM microscopy, or a surface profiler. The average contents (volume concentration) of metallic particles in the roughness layer varies as a function of the coordinate z normal to the surface. It can be approximated by an exponential function,
where a and K1 are the fitting parameters.
Two separate regions of effective roughness dielectric can be considered:
Region I: 0p, where the concentration of metallic inclusions is below the percolation threshold, i.e., where the mixture remains in the dielectric phase; this is the region adjacent to the dielectric matrix of the PCB. Herein, Tp is the distance within the layer at which percolation is reached.
Region II: Tp, where the concentration of metallic inclusions is higher than the percolation threshold; this is the region adjacent to the smooth foil level and is conducting. Herein, T is the entire thickness of ERD layer. It includes,
where ΔT is the thickness of the region above the percolation.
The concentration , at which percolation will occur for the metallic particles in the roughness dielectric layer, can be obtained empirically, i.e., estimated from the microscopy pictures, or from the profiler data. By solving the equation,
with respect to Tp, one can get the height of the dielectric phase of ERD.
First, let us consider the region 0p. This is the dielectric layer with relative permittivity varying according to the profile function (1) from the matrix dielectric properties em (at z=0) to the final pre-percolation value ep (at z=Tp). Since dielectric function varies with z as,
The effective permittivity of such a layer can be calculated through the equivalent partial layered capacitor consisting of series connection of sublayer capacitors. The capacitance of the resultant capacitor with variable properties of the dielectric is,
where C0 is the capacitance of the corresponding air-filled rectangular parallel-plate capacitor of thickness, d. Herein, d = Tp.
The effective dielectric properties of such dielectric layer can be easily derived from (5) as
This permittivity is complex,
If the imaginary part is represented through the equivalent conductivity, the corresponding equivalent conductivity is,
This conductivity will not be high, because it is coming from a lossy effective roughness dielectric in the dielectric phase. Its value is on the order of 10-2 S, which is similar to a comparatively lossy dielectric.
However, in Region II, the conductivity increases exponentially towards smooth copper level until it reaches the conductivity of the pure copper used on a PCB. Therefore,
where K2 is the exponent parameter for conductivity after percolation, and it can be solved from the equation, when σp reaches the level at the beginning of percolation, e.g., σp = 0.01σCu. Percolation threshold is assumed to be 25% of volume concentration of metallic inclusions in the epoxy-resin fiber-filled dielectric matrix . As a reminder, T is the entire thickness of the ERD layer.
Then the conductivity profile function with respect to the coordinate z will be,
The dielectric profile function in the second conducting layer will be defined as,
The effective permittivity of the two lossy dielectric layers is calculated through the equivalent capacitor containing two capacitors in series. Both capacitors have gradient fillers. The filler of the first layer is in the non-conducting dielectric phase, and the other is close to percolation, i.e., conducting phase.
From (12), separating real and imaginary parts, the following ERD parameters can be calculated: DKr = εeff’ and DFr= tan δeff = εeff’'/εeff’.
Metal Inclusion Profiles in Different Foils
Cross-sectional microscopic (SEM or optical) analysis is used to characterize roughness profile of the foil. For this purpose, typically a signal trace is cut perpendicular to the direction of the electromagnetic wave propagation. The procedure of image processing is described in detail in [17,18,19]. An example of a binary (black-and-white) image of the trace cross-section of VLP foil on PPO Blend substrate is shown in Figure 1. The bottom ("foil", or "matte") side of this foil is rougher that the top ("oxide", or "drum") side.
Figure 1: Binary image of the cross-section of the signal trace of black oxide VLP foil on PPO blend substrate.
The surface roughness profile can be extracted and then quantified using digital image processing based on the analysis of pixels . The average peak-to-valley magnitude of the roughness profile corresponding to the bottom of Figure 1 is shown in Figure 2.
Figure 2: An example of foil roughness profile extracted from the bottom side of the binary image.
Foil surface roughness has the stochastic nature, therefore, along with peak-to-valley values, it can be characterized it in terms of the probability density function (PDF) and autocorrelation function (ACR). Corresponding PDF and ACR curves for VLP foil type are presented in Figure 3. The PDF shows that copper foil surface roughness has normal (Gaussian) distribution, and from ACR it is clearly seen that the roughness is uncorrelated and does not contain any periodicity.
Figure 3: Probability density function histogram (a) and autocorrelation function (b) corresponding to roughness profile in Figure 2.
In many cases (though not always), surface roughness is isotropic, i.e., the PDF is invariant with respect to any direction of the wave propagation. Since the parameters of PDF can be obtained from the profile, the roughness 3D profile can be reconstructed for the future investigation using, for example, Gaussian filter, or any other low-pass filter widely used in digital image processing. The parameters of this filter should be adjusted to get the best correlation with the measured roughness profile .
Figure 4: 3D roughness profile surface generated using PDF and Gaussian filter.
The PDF and ACR of the generated 3D roughness profile shown in Figure 4 agree well with those shown in Figure 3. The 3D generated roughness profiles are useful for roughness quantification, e.g., as in , , including ERD design curves , as well as for metallic concentration variation study needed for equivalent capacitance approach.
Applying the same image processing technique as for the roughness magnitude extraction, but performing summation for each column of pixels, one can get the volume concentration of metallic inclusions in the transition between pure dielectric to pure metal. Figure 5 shows the function for different types of foils. It is seen that 0% concentration corresponds to dielectric matrix, while 100% to smooth copper. The transitions are comparatively smooth – the left-hand front corresponds to the foil side, and the right-hand side to the "oxide" side. The smoother the conductor side, the more abrupt the metallic concentration slope is.
Figure 5: Volume concentration of metallic inclusions in black oxide STD (a), VLP (b), and HVLP (c) foil on PPO blend substrate.
The profiles on the foil and oxide sides can be fitted using exponential or polynomial functions as is shown in Figures 6-8. For simplicity of calculating integrals analytically in (5), (6), and (12), the exponential approximation will be further used. Note that the parameter b herein is the same as K1 in (1). The approximation data for a number of studied samples of black-oxide foils on PPO Blend substrates are presented in Table 1. The parameter δrms herein is the root-mean-square error at the approximation.
Figure 6: Approximation of volume concentration of metallic inclusions as a function of D distance from the smooth conductor: "foil" side (a) and "oxide" side (b) on STD foil.
Figure 7: Approximation of volume concentration of metallic inclusions as a function of distance from the smooth conductor: “foil” side (a) and “oxide” side (b) on VLP foil.
Figure 8: Approximation of volume concentration of metallic inclusions as a function of distance from the smooth conductor: “foil” side (a) and “oxide” side (b) on HVLP foil.
Table 1: Exponential approximation of profile functions on “foil” and “oxide” sides of copper foils.
Calculation of ERD Parameters Using the Proposed Analytical Model
The proposed equivalent capacitance model was applied to calculate the ERD parameters of the three types of foils as in Table 1. Figures 9-11 show the calculated frequency dependences for DKr and DFr of the corresponding ERD layers. The thicknesses of the layers are also determined from the metallic concentration profiles. Note that in the previous publications , , , , the ERD parameters were independent of frequency. However, the new analytical model shows that there is frequency dependence. The ERD parameters for the STD foil on its “foil” and “oxide” sides differ significantly because the “foil” side is much rougher than the “oxide” side. The corresponding differences for the sides on the VLP and HVLP foils do not differ that much, though they are not equal. Though the extracted ERD parameters for the VLP foil herein are close to those of the HVLP, the thicknesses of the layers to be modeled differ: the HVLP layers are thinner than VLP. Note that the calculated ERD results are not the same as reported in , because the test samples studied herein are different from those in .
In the present study, the roughness parameters of HVLP and VLP samples are not much different, while in  the VLP and HVLP foils are quite distinct.
Figure 9: Effective roughness dielectric parameters as functions of frequency for STD foil: DKr (a) and DFr (b).
Figure 10: Effective roughness dielectric parameters as functions of frequency for VLP foil: DKr (a) and DFr (b).
Figure 11: Effective roughness dielectric parameters as functions of frequency for HVLP foil: DKr (a) and DFr (b).
Numerical Simulations Based on Analytically Calculated ERD
The measured insertion loss |S21|, dB and time delay t on a transmission line, i.e., a single-ended stripline, increase as conductor roughness magnitude increases, and hence, the values DKr and DFr of the corresponding ERD layers increase. This is illustrated by Figure 12.
Figure 12: Insertion loss (a) and time delay (b) on 16-inch stripline with PPO blend dielectric and different foil types.
The delay time increase as conductor roughness increases is the direct consequence of the capacitive (dielectric) nature of the ERD. Since phase progression in a TEM transmission line of the length land with the homogeneous dielectric filling εr is ,
the corresponding time delay is calculated as,
The corresponding insertion loss on the line is approximately
where the total loss constant α for the TEM mode on the line is comprised of the conductor and dielectric loss parts ,
Note that herein εr is the dielectric constant (real part of permittivity) of the effective dielectric inside the transmission line, which includes both the substrate dielectric matrix and ERD.
Model Setup for Numerical Simulations
Similar to the previous studies , the stripline simulation numerical electromagnetic model has been created. It includes the dielectric matrix material characterization of the substrate dielectric obtained through the extrapolation DERM technique as in , , and thin layer-like objects representing conductor surface roughness as the ERD: above the trace (“foil” side) and below the trace ("oxide" side). The corresponding ERD layers are also placed on the reference (ground/return) planes. Figure 13 shows a cross-sectional view of the numerical model setup. The line length of the stripline structure was 391.414 mm (15.4 inches); stripline traces were 17.5 mm thick (0.5-oz copper) and 340 mm (13.5 mil) wide. The impedance of the single-ended line was 50 Ω. Cross-sectional dimensions for all the three test lines were identical, except for the foil roughness. Since the length of the modeled line is comparatively long, to make the models more computationally efficient, each model was subdivided into two equal segments, and then cascading of the corresponding ABCD matrices was done.
Figure 13: Numerical model setup.
Numerical Simulations Results with Homogenized Frequency-dependent ERD
The models were simulated using the Finite Integral Technique (FIT), a time domain solver . Time domain solvers are suited to capturing phase results across wide frequency bands. A mesh size in the models was about 2 million cells. The waveguide ports were used for excitation. The measured and modeled data are shown in Figures 14-16. The dielectric parameters of the homogeneous ERD layers in these models are as shown in Figures 9-11. The agreement of the modeled and measured results for all the three test scenarios with STD, VLP, and HVLP foils validate the proposed analytical approach. The high-frequency behavior is captured better as compared to the non-dispersive models as in ,  due to the frequency-dependent DKr and DFr parameters extracted using the equivalent capacitance ERD model.
Figure 14: Measured and modeled S21 results for a stripline structure with STD foil.
Figure 15: Measured and modeled S21 results for a stripline structure with VLP foil.
Figure 16: Measured and modeled S21 results for a stripline structure with HVLP foil.
Numerical Model of Layered ERD Structure
Another way of roughness dielectric numerical modeling was also tested. The “layered” model was set up in the same way as the other models with the only one difference. The foil layer is specified differently from the previous models with homogeneous ERD parameters. In the "layered" model for the STD foil, the roughness dielectric properties are split into three parts: the top 1/3rd part (close to metal) has independent of frequency DKr = 16, the middle 1/3rd part has DKr= 12, and bottom 1/3rd part (next to matrix) has DKr =8. DFr is set as 0.17 in all the three sublayers. In this case, each sublayer is very thin, adding significant mesh count and therefore increasing simulation time.
However, herein, when space mapping for the “layered” model is applied, the object is not split into three separate layers/objects with homogeneous dielectric constants, but the object material properties change depending on the position within the object according to the specified "space map". Note that a "space map" based model does not introduce a new kind of material, but is used to define, for a normal (or anisotropic) material, a generic spatial distribution. This allows for modeling complicated and arbitrary materials. In this work, the ERD itself is specified this way within the matrix material.
In Figure 17, the measured phase is compared to the modeled using “space map” of the ERD layer. The tested cases are the dielectric constants of all three ERD sublayers having first DKr =12; then all of them having DKr =16; and finally, the “layered” roughness dielectric “space map” object with three different DKr values defined consequently. Loss tangent DFr=0.17 in all the layers. Phase results are chosen for comparison because they are the most sensitive to the model parameters choice. As Figure 17 shows, there is an excellent agreement between the measured and the layered model results. From Table 2, the difference between these two results is indeed small (within a few degrees) when compared to the overall phase.
Figure 17: The phase of measured and modeled structures over a narrow frequency band of ~24–26GHz; ERD with DKr=12, with DKr=16, and with space map layered structure.
Table 2: Phase of analytical and layered ERD model at a number of frequencies.
In this work, an analytical model to calculate effective roughness dielectric (ERD) parameters for conductor surface roughness of a PCB foil is presented. Based on the microscopic analysis of the roughness profile, a concentration dependence of metallic inclusions in the transition between the ambient dielectric matrix and copper is obtained. Using such a concentration dependence, the equivalent capacitance associated with the roughness layer is calculated analytically. Then the parameters of the effective roughness dielectric are extracted from this equivalent capacitance. The ERD parameters obtained from the analytical model are frequency dependent unlike in the previous works; therefore, they describe the high-frequency behavior (at data rates of a few dozen Gbps) of PCB interconnects more accurately than the frequency-independent models. The proposed model is applied to three stripline test scenarios with three different types of foils—STD, VLP, and HVLP, and is validated by an excellent agreement between the full-wave FIT numerical modeling and measurements. Two types of numerical models are obtained: using homogeneous effective roughness dielectric and using space mapping when modeling a "layered" ERD. The "layered" ERD provides the closest to the measured result when S21 phases are compared.
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This paper, with original title “Equivalent Capacitance Approach to Obtain Effective Roughness Dielectric Parameters for Copper Foils,” was first presented at the 2018 IPC APEX EXPO Technical Conference and published in the 2018 Technical Conference Proceedings.
* Marina Koledintseva was with Oracle during the writing and presentation of this paper.