Mentor Discusses New DFT, DFM, and Design Verification Tools


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At electronica 2018, John McMillan, digital marketing program manager-Electronic Board Systems, and Mark Laing, business development manager-Valor Division of Mentor, a Siemens business, discuss new tools for PCB design verification, as well as design for manufacturing (DFM) and design for testing (DFT).

Pete Starkey: I’m very pleased to meet both of you gentlemen. Many thanks for joining me. John, I’d like to ask you first about design verification. Designers often see issues late in the design process. How can you help identify and fix them?

John McMillan: Yes, there are areas throughout the design flow where errors are encountered that typically get through. You don't discover them until maybe assembly or manufacturing, or when a bare board comes back. Discovering them at those late times is a huge cost. A re-spin is very expensive, and when it affects time to market—especially in competitive things like cellphones and those kinds of fast-paced consumer product industries—it can make or break a product's sales if you don’t hit the market on time. So, we have brought functionality that brings those checks that normally take place after, to avoid the mistakes that are typically found out after the fact by being able to check those before we go on to the different parts of the design flow.

JohnMcMillan100.jpgSome examples of that are electromechanical co-design and ECAD collaboration when companies find problems with circuit boards such as misaligned mounting holes, physical interfaces, or connectors that come through housings and chassis. They can now do integration where they bring the MCAD into the actual PCB tool and bring in step models of the enclosures, brackets, and non-electrical parts, and check for clearance violations to ensure there are no surprises. They don’t have to re-spin a board or redesign something to do that using a collaborative, co-design product flow.

Also, other things you can find when boards are being tested is there are always times where you may find shorts or signal integrity issues you didn't expect. Thus, that “shift-left” type of verification is also something we can now do as early as a schematic design where traditionally there has not been validation for that. In a schematic, through our acquisition of Valydate, we can run checks that catch a lot of the issues that you may encounter or not discover until it’s too late. Now, you can run these schematic checking routines that will enable you to go back with model intelligence, find the missing links and disconnects and ensure connectivity is correct and first pass design success is achieved.

Starkey: Are these routines and procedures built into the system or do they rely on the designer to know when to actuate them or operate them?

McMillan: That's a great question because many designers may be working on a schematic, such as a hierarchical design. Some may wait until the end, but you can also do these checks along the way and run checks intermittently to check as you go along. It's not like you wait until the end and find out you made a mistake; you can execute checks throughout the design process. Over 150 schematic checks are built-in as well as an extensive model library. As we know, the schematic is the foundation for product designs, so having the design correct from the earliest stages sets the stage for product design success throughout the rest of the design cycle.

Starkey: But it's really down to the designer's decision as to what checks to run and at what point in the process to run them.

McMillan: Yes, we include over 150 of them; they can actually create their own rules too. As it learns, it grows. But yes, it's up to the designer to define a stopping point where they decide they want to run a check on it. Before they hand it off—definitely to layout—they're going to want to run the validation on the schematic.

Starkey: Is what you're offering now something new that wasn’t available in the past?

McMillan: Yes, it's very unique to us. We did it through our acquisition of Valydate, a company we integrated into our front-end tool to give that extra level of functionality to do schematic validation in our tool flow.

Starkey: What's been the uptake on it so far?

McMillan: The response has been great. The checks have added immeasurable value. The feedback we’ve received shows its finding errors that would have otherwise been missed.

Starkey: You're saving some very expensive mistakes, or in some cases, catastrophic mistakes from the point of view of new product introduction.

McMillan: Absolutely. We get the same feedback from our collaboration piece for MCAD—being able to bring the MCAD into that—and also with the co-design through our step model imports as well. All of these shift-left capabilities, essentially creating a digital twin of the electronic product ensures first-pass design success of best in class products. It eliminates design re-spins, reduces costs and ensures time-to-market targets are achieved.

Starkey: John, is there anything more you’d like to add?

McMillan: This shift-left product design approach also carries through to DFM—for example, the test points—you go into Mark’s area for the DFM/DFA/DFT, and you can see how it also reels back into the layout.

Starkey: Mark, can I ask you to bring me up to speed on DFM and DFT? What new facilities can you offer to make the job easier and more successful?

mark_laing.jpgMark Laing: Yes; thanks, Pete. Let's start with testability. That is a classic environment at the moment where that area is focused very much after the fact. A lot of the customers don't consider testability as part of the design process at all.

Starkey: Just to be clear, are we talking about testability at the bare board stage, the assembly stage, or both?

Laing: It's mostly at the assembly stage. Most customers will do a functional test, which is a very good way to prove that a product is working correctly. However, it's not an efficient way to determine that the product's been built correctly and that no opens or shorts or component issues are occurring. Achieving good testability in the assembly area relies on the design. If the design is not conducive to that testability strategy, then it's going to be suboptimal, and that's not good.

Starkey: How do you create the terms of reference and the design rules?

Laing: What we want to do is to left-shift that into the schematic to start, not just left shift into the layout process; it has to start with the schematic. It's an evolution of what John was talking about with schematic verification where you're actually validating the design. Here, we're validating the testability of the schematic. We can take that information and knowledge, and then push it forward into the layout process as constraints. The layout is all about constraints—constraints of performance, the board, and all of the different performance requirements. We're adding the testability to that so we can implement that testability into the design; when it comes out, it's much more conducive to accurate testability in manufacturing. That segues into DFM as well. If you go back 15 years, DFM was a classic post-design process. Valor started their business by analyzing Gerber files.

Starkey: I can recall the beginnings of Valor at a time when I was a PCB fabricator. At that time, it was difficult to get a designer to recognize how these things were actually made. They thought you just got this big black box, put the Gerbers in one end, and the boards came out the other end. They didn't appreciate the realities of the manufacturing process.

Laing: Absolutely, and that's something where the industry has made some good improvements over the last five to six years. We've taken something that was very much that post-process, and it would not be unusual to get hundreds or even thousands of errors generated from that analysis. To be able to take that and go back into the design and say, “Make all of those changes,” it’s nearly impossible. The classic answer would be, “Tell me the top five things I can change because it's just too much and the cost of change is just too significant.” We’ve broken that down and run it concurrently through the layout process. You might run some analysis at component placement and start to run analysis on the initial routing phases as the design is finalized. We've taken something that was run significantly at the end and broken it down and run it in multiple ways through the design process. It makes it much easier—if we find a problem at that point—to correct it and move on. When we get to the end, we have something now that's much more manufacturable and easier to assemble and test.

Starkey: And you're doing it on the design side of the CAD/CAM interface. Again, in my day, you would receive the design. If you had the benefit of a competent front-end system and a front-end engineer, you would run your design checks, which would flag a lot of potential manufacturability problems. Then, you would go back to the designer and say, “Look, I found this, this, and this, which are likely to cause yield problems in manufacturing.” Effectively, you're preempting that by handing over a clean design at that CAD/CAM interface.

Laing: Exactly. And we're doing that from a design verification, testability, and DFM perspective. Who owns the design? It’s the designer, which allows them to supply a PCB that meets all of the specifications. It’s not just about the fact that it's been designed well, but that it also will be manufactured correctly.

Starkey: That's right. Thanks very much for your time, Mark and John. It's very busy out on the show floor, and I appreciate that you interrupted your schedule to talk with me.

Laing: Thanks, Pete.

McMillan: Thank you.

Visit I-007eBooks to download your copies of Mentor’s books today: The Printed Circuit Designer’s Guide to… Signal Integrity and Power Integrity by Example.

 

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