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The challenges faced by the PCB designers of today are significant. If we examine the breadth of designs, we find ever-increasing data rates and more high-speed signal routing that drive additional challenges meeting signal-quality requirements, including reflection signal loss and crosstalk issues. At the same time, designers are being asked to complete designs in shorter cycle times and in smaller form factors. They must come up with new and more complex routing strategies to better control impedance and crosstalk. Manual implementation is often time-consuming and prone to layout errors. Designers have an increased need for pre-layout simulation to evaluate the design early on and establish routing strategies.
Designers are faced with conflicting requirements. The PCB designer is expected to do more with less space. The overall density of designs is increasing. Balanced against cost constraints, the PCB designer may leverage high-density interconnect (HDI) technology to compress the design into the available space, which in turn increases the likelihood of signal integrity issues. Cost pressures may force the PCB designer to reduce layer count or, at the very least, stay within the layer count that has been budgeted.
The PCB designer finds himself in a constant battle to converge on a design that meets all the design constraints. EDA vendors have provided a suite of various tools and automation to assist with the manufacturing constraints and physical and signal integrity physics of the design—breakout tools, route feasibility and estimation, timing and delay match, HDI-compliant design, and flex and embedded component design. Without a doubt, the challenges are significant for the PCB designer. If the constraints cannot be surmounted with technology, perhaps the solution is to work smarter.
So, rather than looking at some of the advanced additive technologies and other PCB manufacturing capabilities that could enable us to work at a significantly finer pitch, albeit at a higher cost, let’s focus on those capabilities that allow us to work smarter. As an IC packaging EDA engineer, I argue that working collaboratively with the system design and packaging engineers is one way we can enable denser designs that are completed faster, while still meeting signal integrity and power integrity requirements. Doing so requires more pre-planning and pre-analysis of the design, specifically looking at breakout patterns from the high pin-count devices, the critical signal typologies and routing schemes, and an up-front analysis of the critical signals within the design.
To read this entire article, which appeared in the August 2018 issue of Design007 Magazine, click here.