Achieving Optimum Signal Integrity During Layer Transition on High-Speed PCBs


Reading time ( words)

This article discusses the impact of stitching vias and discontinued return path or reference on signal integrity during layer transition on high-speed PCBs, particularly in terms of signal reflection and crosstalk.

Introduction

In electronic systems, signal transmission exists in a closed-loop form. The forward current propagates from transmitter to receiver through the signal trace. Meanwhile, the return current travels backward from receiver to transmitter through the power or ground plane directly underneath the signal trace that serves as the reference or return path. The path of forward current and return current forms a loop inductance.

It is important to route the high-speed signal on a continuous reference plane so that the return current can propagate on the desired path beneath the signal trace. In addition to that, whenever there is signal transition from one layer to another through a via, an extra via that connects the reference planes on different PCB layers (i.e., stitching via) must be placed near the signal via to provide a continuous return path.

If the return path is broken due to the absence of a stitching via or switching of reference plane from ground to power or vice versa after layer transition on PCB, the return current might detour and propagate on a longer path, which causes the rise of loop inductance. This might also lead to the sharing of common return path by different signals that poses high risk of interference among the signals due to higher mutual inductance. This interference results in crosstalk that occurs on the transmitted signal. This phenomenon is proven in the following section with 3DEM simulation.

Analysis of signal reflection and crosstalk with 3DEM modeling

To investigate the impact of stitching via and discontinued return path on high speed signal fidelity, three test models of 3DEM are constructed using Keysight EMPro. In test case 1, two signal traces with 50 ohm characteristic impedance in single ended mode on top PCB layer are transitioned to bottom layer using vias. Each segment of the signal traces on both top and bottom layers is 100 mil long and 5 mil wide. Meanwhile, the diameter of the via barrel and pad is 5 mil and 7 mil respectively.

To read this entire article, which appeared in the June 2018 issue of Design007 Magazine, click here.

Share


Suggested Items

Dave Wiens Discusses Multi-board Design Techniques

07/09/2018 | Andy Shaughnessy, I-Connect007
For our multi-board design issue, I interviewed Dave Wiens, product marketing manager for Mentor, a Siemens business. We discussed how the multi-board design technique differs from laying out single boards, along with the planning, simulation and analysis processes required to design multi-board systems.

Paving the Way for 400Gb Ethernet and 5G

06/26/2018 | Chang Fei Yee, Keysight Technologies
This article briefly introduces the 4-level pulse amplitude modulation (PAM-4) and its application in 400 Gigabit Ethernet (400GbE), to support the booming data traffic volume in conjunction with the deployment of 5G mobile communications. Furthermore, this article also highlights the essential pre-layout effort from signal integrity perspective for physical (PHY) link design on a PCB, including material selection, transmission line design and channel simulation to support 56Gbps data rate that paves the way for seamless communication in 400GbE.

Fadi Deek Discusses Mentor’s New Power Integrity eBook

04/22/2018 | Andy Shaughnessy, Design007 Magazine
At DesignCon 2018, I ran into Mentor’s Fadi Deek, the author of both of Mentor’s I-Connect007 eBooks: the newest, "The Printed Circuit Designer’s Guide to Power Integrity by Example," and their first book, "The Printed Circuit Designer’s Guide to Signal Integrity by Example." We sat down and discussed how the idea for the books came about, as well as some of the power integrity challenges facing PCB designers and engineers.



Copyright © 2018 I-Connect007. All rights reserved.