Paving the Way for 400Gb Ethernet and 5G


Reading time ( words)

This article briefly introduces the 4-level pulse amplitude modulation (PAM-4) and its application in 400 Gigabit Ethernet (400GbE), to support the booming data traffic volume in conjunction with the deployment of 5G mobile communications. Furthermore, this article also highlights the essential pre-layout effort from signal integrity perspective for physical (PHY) link design on a PCB, including material selection, transmission line design and channel simulation to support 56Gbps data rate that paves the way for seamless communication in 400GbE.

I.  Introduction

400GbE is a new wired communication standard to accommodate the booming data traffic volume with the implementation of 5G mobile communications. In the implementation of 400GbE communication, electrical interface with 4-level pulse amplitude modulation (PAM-4) signaling over 8 lanes is adopted. The communication of eight lanes at 56Gbps (i.e., 28GBaud) per lane enables the total bandwidth of 400Gbps over the Ethernet. The electrical specifications of 400GbE with PAM-4 signaling are defined in IEEE 802.3bs.

PAM-4 has 4 digital amplitude levels, as shown in Figure 1. It has an advantage over non-return-to-zero (NRZ) signals because each level or symbol in PAM-4 contains two information bits providing twice as much data throughput for the same baud rate. For instance, 28GBaud is equivalent to 56Gbps in PAM-4 and 28Gbps in NRZ respectively.

II.  Essential pre-layout effort from signal integrity perspective

According to guidelines, a PAM-4 channel with trace length up to 8 inches on a PCB shall have insertion loss less than 10dB at 14GHz (i.e., Nyquist frequency of 28GBaud) and 20dB at 28GHz (i.e., 2nd harmonic of 28GBaud) respectively to achieve seamless data communication between the transceivers.

To read this entire article, which appeared in the May 2018 issue of Design007 Magazine, click here.

Share


Suggested Items

Moving From 28 Gbps NRZ to 56 Gbps PAM-4: Is it a Free Lunch?

09/19/2018 | Yuriy Shlepnev, Simberian
The usual way of signaling through PCB interconnects is a two-level pulse, an encoding of 1s and 0s or bits, named NRZ (non-return-to-zero) or PAM-2 line code type. Increasing the data rate with the NRZ code type presents some obstacles. For a 28 Gbps NRZ signal, the bit time is about 35.7 ps with the main spectral lobe below 28 GHz. For a 56 Gbps NRZ signal, the bit time is about 17. 86 ps, with the main spectral lobe below 56 GHz. One can feel the problem already: Getting PCB interconnect analysis and measurements up to 56 GHz and beyond is very challenging, to say the least.

The Impact of PCB Dielectric Thickness on Signal Crosstalk

08/27/2018 | Chang Fei Yee, Keysight Technologies
Crosstalk is an unintentional electromagnetic (EM) field coupling between transmission lines on a PCB. This phenomenon becomes a major culprit in signal integrity (SI), contributing to the rise of bit error occurrence in data communications and electromagnetic interference (EMI). With the existence of mutual inductance and capacitance between two adjacent transmission lines on a PCB, crosstalk has become more severe due to the shorter signal rise/fall times at today’s higher data speed rates.

Advanced Stackup Planning with Impedance, Delay and Loss Validation

08/02/2018 | Yuriy Shlepnev, Simberian
A typical PCB design usually starts with the material selection and stackup definition—the stackup planning or design exploration stage. How reliable are the data provided by the material vendors and PCB manufacturers? Can we use these data to predict trace width and spacing for the target trace impedance or to calculate delays or evaluate the loss budget?



Copyright © 2018 I-Connect007. All rights reserved.