Reading time ( words)
There’s a lot of talk about the 3rd generation of Double Data Rate memory known as DDR3. We at Nine Dot Connects have laid out several DDR3 boards in the past three months. There is quite a bit of detail to know about DDR3 design and layout and unfortunately, there is also a lot of misinformation out there. We have waded though and analyzed the literature. We wish to share our findings and understanding with you in our latest webinar series, Double Data Rate (DDR3) Shouldn't be Double Trouble.
In our two-part series on this topic, we will first cover key concepts necessary for proper signal integrity and general DDR3 design. Topics to be covered this month are:
- Brief history of the DDR concept
- Comparison between the different generations of DDR
- The signaling and timing requirements for DDR3
- Understanding match length versus match delay
- Compensating for typical routing delay
- Using the iCD Stackup Planner to assist in delay matching calculation
In part 2, we will build upon this foundation by demonstrating the practical aspects of DDR3 layout techniques.
This latest webinar, Double Data Rate (DDR3) Shouldn't be Double Trouble, is scheduled for January 31, 2018 at 2 pm Eastern Time. For more information and to register, click HERE.
Andy Shaughnessy, I-Connect007
For our multi-board design issue, I interviewed Dave Wiens, product marketing manager for Mentor, a Siemens business. We discussed how the multi-board design technique differs from laying out single boards, along with the planning, simulation and analysis processes required to design multi-board systems.
Chang Fei Yee, Keysight Technologies
This article briefly introduces the 4-level pulse amplitude modulation (PAM-4) and its application in 400 Gigabit Ethernet (400GbE), to support the booming data traffic volume in conjunction with the deployment of 5G mobile communications. Furthermore, this article also highlights the essential pre-layout effort from signal integrity perspective for physical (PHY) link design on a PCB, including material selection, transmission line design and channel simulation to support 56Gbps data rate that paves the way for seamless communication in 400GbE.
Dave Lackey and Anaya Vardya, American Standard Circuits
The design process is arguably the most important part of the flex circuit procurement process. The decisions made in the design process will have a lasting impact, for better or worse, throughout the manufacturing cycle. In advance of providing important details about the actual construction of the flex circuit, it is of value to provide some sort of understanding of the expected use environment for the finished product.