Reading time ( words)
There’s a lot of talk about the 3rd generation of Double Data Rate memory known as DDR3. We at Nine Dot Connects have laid out several DDR3 boards in the past three months. There is quite a bit of detail to know about DDR3 design and layout and unfortunately, there is also a lot of misinformation out there. We have waded though and analyzed the literature. We wish to share our findings and understanding with you in our latest webinar series, Double Data Rate (DDR3) Shouldn't be Double Trouble.
In our two-part series on this topic, we will first cover key concepts necessary for proper signal integrity and general DDR3 design. Topics to be covered this month are:
- Brief history of the DDR concept
- Comparison between the different generations of DDR
- The signaling and timing requirements for DDR3
- Understanding match length versus match delay
- Compensating for typical routing delay
- Using the iCD Stackup Planner to assist in delay matching calculation
In part 2, we will build upon this foundation by demonstrating the practical aspects of DDR3 layout techniques.
This latest webinar, Double Data Rate (DDR3) Shouldn't be Double Trouble, is scheduled for January 31, 2018 at 2 pm Eastern Time. For more information and to register, click HERE.
Kelly Dack, CID+, EPTAC
Working for an EMS provider, I am often asked to make sense of customers’ PCB design data packages that must be audited for completeness and manufacturability. Quite often, EMS operations receive data to produce a PCB design and begin the auditing process, only to be called off due to customer changes. Sometimes the data is incomplete, or it is missing one or more of the data files required to fabricate the PCB at the supplier. There are also occasions where a customer has sent files that were supposed to be the updated version but were not changed at all.
Andy Shaughnessy, Design007 Magazine
When we started planning this issue on design data, I knew we’d have to speak with PCB designer and EPTAC design instructor Steph Chavez. In this interview, he explains some of the biggest issues related to good design data handoff, and he offers some ways forward.
Dan Beaulieu, D.B. Management Group
Over the course of his career, Mark Thompson, CID+, engineering support at Prototron Circuits, has evaluated thousands of data packages and delivered numerous talks to designers and engineers about how to create the perfect package. In the spirit of “garbage in, garbage out,” data packages must be perfect to create quality boards. Learn all this and more in The Printed Circuit Designer’s Guide to… Producing the Perfect Data Package!