Reading time ( words)
It's easy to verify constraints for clearance, high-speed, fabrication, maximum via count, and testability constraints in PADS. Set up, save, and use verification schemes as you see fit.
Violations can be viewed in an intuitive spreadsheet with just two mouse clicks. Select a rule violation from the spreadsheet to automatically zoom in and correct the violation and quickly re-verify that the violation has been corrected.
This video demonstrates how you can use a highly customizable spreadsheet interface to quickly set up verification schemes and view rule violations.
Click here to watch the video.
Real Time with...IPC
During IPC APEX EXPO 2018, Polar Instruments' Lupita Maurer and Geoffrey Hazelett sat down with Editor Andy Shaughnessy to discuss upgrades to their SpeedStack tool and Lupita's new position with the company.
Altium recently conducted its first-ever users conference, AltiumLive 2017: Annual PCB Design Summit, at the Hilton Resort and Spa in San Diego. Speakers included Dan Beeker of NXP Semiconductors, Max Seeley of 3M Corporate R&D, Tara Dunn of OMNI PCB, Susy Webb of Fairfield Nodal, Charles Pfeil of Altium, and our own Happy Holden. This conference drew hundreds of PCB designers, and included a robot design challenge and battle. If you couldn’t make it, don’t worry. We shot a variety of video and still photos.
One of the most common outputs from a DC Drop simulation is a current density plot. But how much is too much current density? The answer depends on temperature rise, and requires a PI-thermal co-simulation to properly characterize.