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This Mentor white paper, originally presented at DesignCon and nominated for a best paper award, includes an investigation of DDR4's Pseudo Open Drain driver and what its use means for power consumption and Vref levels for the receivers.
This paper also examines a DDR4 system design example and the need for simulating with IBIS power aware models versus transistor level models for Simultaneous Switching Noise characterization.
To download this paper, click here.
Pete Starkey, I-Connect007
Altium held a very successful AltiumLive PCB Design Summit in San Diego, California at the beginning of October for the benefit of their North American design community, and followed it three weeks later with a counterpart European event in Munich. And what an eye-opener it proved to be—literally hundreds of delegates, a superbly organised and managed programme, billed as a completely immersive two-day interactive design experience on a theme of learning, connecting and getting inspired.
Vern Solberg, Consultant
Technology and processes for embedding capacitor and inductor elements rely on several unique methodologies. Regarding providing capacitor functions, IPC-4821 defines two methodologies for forming capacitor elements within the PCB structure: laminate-based (copper-dielectric-copper) or planar process and non-laminate process using deposited dielectric materials.
Dingru Xiao, Cadence Design Systems
Advanced PCB design is an iterative process of analysis-fix-analysis. Historically, this process is very time-consuming, requiring analysis experts and PCB designers to work together to find and fix layout problems. This article describes a new PCB design methodology that allows a PCB designer to perform the power design without having to run expert-level analysis tools. This methodology provides the setup automation for advanced analysis without the need to understand every minute parameter, and can be completed in a few steps.