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The Orange County Chapter of the IPC Designers Council is holding a Lunch ‘n’ Learn event on April 19 at JT Schmid’s Restaurant & Brewery in Anaheim. This meeting features two speakers and takes place from 11:30 am - 1:30 pm in the Regan Room at JT Schmid's.
The first speaker is Cuong Nguyen, Field Applications Engineering Manager with EDA Direct. His presentation is titled "High-Speed DDR4 Memory Design and Power Integrity Analysis: What designers need to know to achieve the best performance with DDR4."
DDR4 is an entirely new memory architecture with higher bandwidth, lower power consumption, and higher memory capacity. Incorporating DDR4 memory interfaces in today’s design poses many challenges for both the EE’s as well as the layout engineers. These high-speed interfaces require careful considerations in terms of optimizing the electrical signaling between sensitive components and to minimize the noise from high switching activities from the memory devices. Layout constraints must be carefully specified to ensure tight timing alignment for clock and strobe signals. In addition, the power distribution network (PDN) also became more fractured to support the many supplies required by current ASIC and FPGA devices. This, an insufficient decoupling for the supplies, can potentially create more noise, crosstalk, and increase the EMI in the system.
In this seminar, we will review the DDR4 architecture, routing topologies, signaling protocols, how it can be simulated on the PCB, and how to maximize PDN designs from a layout perspective. Based on the simulation results, optimizing trace routing, board stackup, component placements, connectors, terminations, and other tradeoffs can be implemented to maximize the performance of your design.
The second speaker is Ammar Abusham, Senior Applications Engineer with Mentor Graphics, presenting "Better PCB Design Using the Fabricator’s View: What designers need to know about DFM verification and its impact on your design." You are an experienced PCB designer using a good CAD flow. So why is it that what appears to be a good design to you and your layout tool always seems to raise a bunch of questions with your fabricator?
Well, the fabricator sees things differently than you. If you’re like most designers, you are very focused on designing a PCB to the electrical and form-factor specifications. And of course, you take pride in how clean your design looks. Your fabricator on the other hand, is mostly paying attention to those aspects of your design which affect yield, costs, and delivery. To avoid any unpleasant surprises in these areas, it might make sense to put yourself in your fabricator’s shoes for a moment and see some of the checking they will perform on your design data prior to committing it to fabrication. To do this, we’re going to step through a typical PCB fabrication process and identify where DFM issues are likely to show up and what the fabricator is looking for.
Reserve a spot on your calendar on Wednesday, April 19 from 11:30 am to 1:30 pm for this educational “Lunch ‘n Learn” meeting event.
JT Schmid’s Restaurant & Brewery (in Regan’s Room)
2610 E. Katella Ave.
Anaheim, CA 92806
Cost: $15 at the door to help cover the lunch cost. Please RSVP no later than noon on Tuesday, April 18.
We look forward to seeing you!