Cadence’s Zhen Mu Discusses Her Power-Aware Analysis Solution White Paper

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Zhen Mu, senior principal product engineer with Cadence Design Systems, and Brad Griffin, product marketing director for Cadence, discuss Zhen’s new white paper, “Power-Aware Analysis Solution.

Andy Shaughnessy: I'm here at DesignCon 2017 speaking with Zhen Mu from Cadence Design Systems. Zhen is the senior principal product engineer for Cadence, and Zhen I understand you recently published a white paper on a complete power-aware PCB analysis solution. Why don't you tell us about it?

Zhen Mu: Basically, what we want the design community to understand is that the rule checking flow in the PCB design world has been followed for many years, and Cadence has been the leader of the constraint driven flow for over 20 years. For example, you have design goal set up, you explore the design space, then you define constraints. After that, you go ahead to the layout, following the constraints, and after that you run rule checking and do simulations for signoff. Then you get your board out.

Zhen Mu Cadence resized.jpgEverybody is using this flow. One of the questions every PCB designer should be asking is if this flow is complete enough to cover all of the potential design problems. Is this flow still valid? Think about it. Specifically, with high-speed parallel bus designs today, problems are not only tied to signal but also to power. Power noise is becoming more and more important, because the budget has become smaller and smaller. The second question PCB designers should be asking is if the design flow is checking for power noise. Are there any rules to do that? If you're examining your rule set, you probably won't find any.

We want to point out that, when we set up the constraints, we don't even have any physical design, right? The stack-up may have been set up, but we typically don't have much more detail about the physical design. So, the rules, for example, the impedance rules, the coupling rules, are all created in a very ideal environment. There is no power effect at all. Later on, when you do the rule checking on the physical design with the PDN, what do you do? Without any new rule checking technology, design teams still apply the same rule set and simply assume that the PDN did not have any impact on the constraints. For example, when you check signal crosstalk, you still assume that trace reference plane is ideal and the only noise is from other signals, not from anything else.

However, when you have the final design, the plane is there, and the power can bounce because via noise passing through the plane canvas, and then it can destroy all the assumptions associated with the initial constraint. So now if you think about it, when you do the checking at the verification stage, the rule checking or constraint checking, they don't seem to be sophisticated enough for modern PCB designs. You miss all this power and power-induced noise. You have no rules to check for it. It looks like the flow we have been using is running out of steam. That is why we created this white paper. We want to emphasize that we need a new flow, we need new rules, and we need new checking methodologies. This is another important point the white paper tries to address: power-aware checking for the physical design phase.

When talking about new rules to check power noise, we know it is not practical at the early design stage because we do not have any planes yet. So, the flow needs to be enhanced towards the middle or the end of design. At this stage, however, it's harder to do simple rule checking when the plane is bouncing. We have to look at the signal and power noise interactions. Now we found we are moving toward simultaneous switching noise (SSN) analysis, but we don’t want put that level of sophistication into a rule checking flow, it is just too complicated.

Now, we can see that we need a new methodology. Fortunately, we can enable that new methodology using Cadence Sigrity technology. The idea is to compromise a little between simple rule checking and complex SSN analysis. When we are at the stage that a design has the planes and the signals all routed, we can apply a fast, simple simulation to screen the board and find signal and power coupling issues. It is simulation-based, but is a lot faster than a detailed SSN analysis methodology. More importantly, it does not require any complex models—we all know PCB designers do not like dealing with models. Based on the results of the new “power-aware” screening, analysis experts can expedite the advanced analysis and will have fewer problems to clean up as they perform the advanced simulation for signoff.

The new flow that we are proposing is that you still have constraints created at the beginning of the design cycle, but you implement a more detailed screening in the middle of the design and towards the end. The new screening captures problems of signal and the power interactions, and gives designers the chance to fix them much earlier in the design phase. I want to emphasize here: The 20-plus-year-old rule checking flow will never be able to find those kinds of power-induced problems. That is the reason I wrote this white paper.

Shaughnessy: So, most of the current tools are not power-aware, is that basically fair safe to say?

Mu: Right. I think this raises a question, because Cadence was the first one to introduce constraint-driven flow 20 years ago, and the industry followed. Now we realize this flow needs to be updated, or enhanced to get power awareness into it. We're the first ones to ask the customers or the designers the question: Do you ever think that the assumption you used to create your constraints is not the same as the final implementation environment? You shouldn't use that assumption. That's why we introduced this new checking methodology.

Shaughnessy: That's interesting. None of the other tools, like field solvers, have a power-aware functionality?

Mu: Some other tools claim that they are power-aware. For example, with power-aware IBIS models support that we introduced several years back, some other companies confused that with a total power aware solution. Power-aware IBIS model support and a complete power-aware solution is not the same thing. A power-aware solution is not limited to components, but also includes interconnect models for chip, package and PCB. In addition, it requires power-aware rule-checking to ease the burden on analysis experts by catching many more problems early in the design cycle. This truly complete power-aware solution is what makes Cadence Sigrity technology unique.

Field solvers are certainly part of it. But, I think the main thing is PCB designers don’t want a detailed field solver solution, where it would be a complicated, nonlinear model. That would be the verification and that would require a lot more effort. Here, between the simple constraint checking or rule checking and complicated final stage of verification, we need a fast screening tool that will be able to check, not only the signal problem, but also the noise problem caused by the power signal coupling. This part is missing today in many other tools.

brad_griffen_name.jpgBrad Griffin: I'll just interject. You know, Zhen is the expert on this and she understands how all the technology works, and the way I see the industry working today is that we’ve spent a lot of time over the last five or six years focusing on this signal integrity expert. Helping them move from an ideal power and ground environment to a power aware solution. The signal integrity experts have had the tools, mostly enabled because of the things Zhen was mentioning, like the hybrid solver that looks at signal power and ground together.

So, that's all been focused on the signal integrity expert. That poor PCB designer that Zhen was talking about, he's been left on the side just to use his old constraint-driven flow and his old rules approach, with no opportunity to look at signal power and ground interactively. So now the fact that we're able to apply the hybrid solver in a rule checking environment, without the complications of setting up all the simultaneous switching noise parameters and everything the expert does, they can actually look at the noise that's induced through vias on the power plane, and how that could affect crosstalk.

Then you can make some decisions like, "Hey, maybe separating these nets is not the best thing to do; maybe bringing them closer together is actually a better thing to do." That is completely counterintuitive to the environment they'd been brought up in all these years. These tools that Zhen's been talking about provide that power-aware rule checking that gives the PCB designer insight and makes that PCB designer a more valuable member of the team. Then, when he hands the design to the expert, the expert's not going to say, "Ah, you shouldn't have moved them apart. You should have moved them closer."

So now they're working more cohesively, and the white paper is a concise way of promoting this new way of PCB and analysis experts working together. So, Andy, we are hoping that as your readers read through this article, many will be downloading it and taking a more detailed look at it.

Mu: The key message is that PCB design teams need to think about how constraints get set up. What are the assumptions? Recognize that the assumption are idealized. Today, designs are much more complex and speeds are much faster, but most design teams are still checking signals with the assumed ideal power and ground. This is very dangerous. The power-aware solution we talked about today is here to help designers understand and avoid the hidden problem caused by power noise, so that they can release their boards with high confidence.

Shaughnessy: Thank you, Zhen. Good to see you, Brad.

Mu: Thank you, Andy.

Griffin: Great seeing you, Andy.

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