SiSoft Discusses Signal Integrity Drivers and Challenges

Reading time ( words)

SiSoft has been developing cutting-edge signal integrity simulation and analysis software for over 20 years now. In the last few years, the company has launched a variety of innovative SI tools that help automate tasks that used to take weeks or months to complete. I recently interviewed CEO Barry Katz via email, and he detailed their customers’ challenges, and some of the market drivers in the world of signal integrity.


ANDY SHAUGHNESSY: SiSoft has rolled out a lot of new features in the 2016 software suite. Tell us about some of your customers’ challenges that lead to these new features. Let’s start with OptimEye.

BARRY KATZ: Integration and GHz signaling is moving signal integrity inside the chips, and radically changing the problem my customer is solving. While it’s still important to carefully route a PCB, achieving clean signaling is increasingly dependent on correctly configuring IC equalization. And that’s no simple task, because as we passed through 10 Gbps, customers were confronted with millions of equalization options. With so many choices, how can you determine which one is optimal?  This is a very different problem than figuring out the value and placement of termination resistors (which have also been integrated). Because customers didn’t have a fast, automated way to optimize equalization configurations, they were adding extraneous components, buying expensive materials, and unnecessarily shortening connections and lowering data rates. There were a lot of growing pains.

OptimEye tackles the configuration optimization problem head-on. Our DesignCon 2016 paper[1] explains how one customer used OptimEye to remove dozens of components while making their links 25% longer with 60% better performance. This illustrates how important optimal equalization implemented as IC register values can be. SiSoft thrives on solving problems like this. It is perfect for us because link optimization is a system-level problem and we hold all the pieces of the puzzle to get it right; it can’t be solved efficiently by the designer of the transmitter, receiver, or passive channel in isolation of the others. Indeed, the millions of configuration choices illustrate that the best thing each designer could do was offer a range of options because they did not know how the connection would eventually be implemented in a system. So, because we see the whole system, it is our job to resolve the settings in an optimal way. And when you do that, a typical link can achieve 100% better performance, as we demonstrated in our OptimEye Webinar, with only a software change. So, you see what I mean when I say SI is moving inside the chips.

SHAUGHNESSY: What sort of time does this save a typical SI engineer?

KATZ: Months. Particularly when designing systems with dozens or even thousands of links. Think of it:  thousands of links and each one has millions of configuration options. How are you going to solve that?  Sounds like a great place for compute power and advanced algorithms to step in, right?  Today’s SI engineer is sweeping through thousands of setting options, measuring the results, and eventually converging on an acceptable choice. That approach requires hours of labor and simulation to resolve a single link while OptimEye finds the answer in seconds. Increasing compute horsepower has enabled a few significant breakthroughs in the history of SI, and this is one of them. Unfortunately, in absence of an automated solution like OptimEye, about half the industry isn’t even trying to solve the problem and letting the ICs use power-up defaults which, because they’re slanted towards worst-case scenarios, deliver terrible performance on a typical link and sometimes don’t even work. So you see why we’ve made significant investment in OptimEye and are excited to make this technology available.

SHAUGHNESSY: Let’s talk about STATify. What were some of the drivers behind it?

KATZ: When we analyze serial links with OptimEye or otherwise, the active Tx and Rx models are typically implemented using the IBIS-AMI standard, which allows a variety of model styles that support different types of analysis. So, interoperability gets interesting when interconnected Tx and Rx models are of different styles, causing some analysis types to yield unreliable results, as we detailed in a paper at DesignCon 2015[2]. So you had to know what you were doing. But now with STATify, everything “just works.” That’s the good news at a high level. Customers can now run statistical analysis with models that don’t support it, and that is quite a few of them, because we “STATifyd” them. This not only enhances usability, but also has advantages when determining equalization schemes because equalized pulse responses are always available. There’s a lot you can tell from a pulse response when you know what you’re looking at. There’s a lot we could say about STATify, like the way it helps predict low-probability errors without simulating lots of bits, but that’s the basics. It’s a unique capability that we add to our list of firsts in the IBIS-AMI space.

SHAUGHNESSY: Your customers are dealing with huge amounts of data when sweeping a pre-layout solution space or simulating thousands of post-layout nets. Why don’t you explain how that’s traditionally been done, and then how it’s done with the data mining/management capability?



Suggested Items

Combatting Thermal Challenges With TRM Software

10/07/2020 | I-Connect007 Editorial Team
Johannes Adam is the creator of a simulation tool called Thermal Risk Management (TRM) used to help PCB designers and design engineers predict hot spots on the board before during layout. He and Douglas Brooks, founder of UltraCAD Design, have used the tool to produce several technical articles and a book on the subject. In this interview, they tackle the biggest misconceptions they see from designers and engineers who deal with thermal management issues.

The Role of EDA Tools in Creating Fab Notes

09/08/2020 | Pat McGoff, Mentor
When discussing fab notes, there’s a lot of focus on what designers should and should not include in the package. But what is the role of EDA tools in this process, and can intelligent data formats streamline the tasks and help eliminate fab notes that are less than fantastic? In this interview, Pat McGoff, market development manager for Mentor, a Siemens Business, speaks frankly about fab notes and what EDA tool companies like Mentor can do to automate this process.

This Month in Design007 Magazine: Dear Designers—Please Include a Sanity Check

08/11/2020 | I-Connect007 Editorial Team
We recently asked Rick Almeida, DownStream co-founder, and Technical Sales Manager Ray Fugitt to discuss why so many fabricators are still receiving (and correcting) inaccurate and incomplete data from their customers. And if fabricators and designers are content with this current process, is it really a problem after all?

Copyright © 2020 I-Connect007. All rights reserved.